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| Video Enhancement Processor AL260 Data Sheets AL260 Amendments 99.10.04 02.12.19 Preliminary version Preliminary version A0.1: (1) Updated from Preliminary version Version B1.0: (1) Updated from Preliminary version A0.2 (2) Add Register Description 03.05.16 THE INFORMATION CONTAINED HEREIN IS SUBJECT TO CHANGE WIHOUT NOTICE. (c)2002,2003-Copyright by AverLogic Technologies, Corp. Version B1.0 2 AL260 Contents: 1. General Description ................................................................................................... 5 2. Function Block Diagram ............................................................................................ 6 3. Features ...................................................................................................................... 6 3.1 General Features .................................................................................................... 6 3.2 Feature Description: .............................................................................................. 7 4 5 6 7 Applications ................................................................................................................ 8 Application Example .................................................................................................. 9 Pin-Out Diagram ....................................................................................................... 10 Pin Definition and Description ................................................................................ 11 7.1 Input Format Table of AL260:.............................................................................. 11 8 General Function Description ................................................................................. 15 8.1 Function Blocks ................................................................................................... 15 8.2 VIU (Video Input Unit)........................................................................................... 15 8.2.1 8.2.2 8.2.3 8.2.4 Input Data Format ......................................................................................... 15 Video Capture and Down Scale Engine ...................................................... 16 Automatic Positioning Registers................................................................. 17 PLL Programming for Memory and Display Clock..................................... 17 8.3 MIU (Memory Interface Unit)................................................................................ 17 8.3.1 8.3.2 DRAM Bandwidth Consideration ................................................................. 17 DRAM Input/Output Windows ...................................................................... 18 8.3 VPU (Video Processing Unit)............................................................................... 18 8.4.1 8.4.2 8.4.3 Video De-Interlaced with Film Detection and Motion Adaptive................. 19 Up Scale Engine............................................................................................ 19 Keystone Up Scale Engine........................................................................... 20 8.4 VOU (Video Output Unit)...................................................................................... 20 (c)2002,2003-Copyright by AverLogic Technologies, Corp. Version B1.0 3 AL260 8.5.1 8.5.2 8.5.3 OSD ................................................................................................................ 22 LUT (Look up table for Gamma Correction and Color Enhancement) ..... 22 Dithering ........................................................................................................ 23 8.5 BIU (Bus Interface Unit) ....................................................................................... 23 9 Register Definition.................................................................................................... 24 9.1 Register Set .......................................................................................................... 24 9.2 Register Description ............................................................................................ 32 10 Electrical Characteristics......................................................................................... 76 10.1 10.2 10.3 10.4 Absolute Maximum Ratings ............................................................................ 76 Recommended Operating Conditions............................................................ 76 DC Characteristics ........................................................................................... 76 AC Characteristics ........................................................................................... 77 11 Timing Diagrams ...................................................................................................... 78 12 Mechanical Drawing- PQFP-208 .............................................................................. 79 (c)2002,2003-Copyright by AverLogic Technologies, Corp. Version B1.0 4 AL260 1. General Description AL260 is a highly integration Video Enhancement Processor which supports video input with multiple video formats then output with De-interlacing and Scaling effects. It can be used for most video conversion and processing applications. AL260 is equipped with a high quality scaling engine that automatically maintains full screen output display, regardless of the resolution of the incoming signals. Applying AverLogic's proprietary scaling algorithm, the primary input video can be scaled up and scaled down independently in horizontal & vertical directions. It also provides film detection, advanced de-interlacing, filtering, and scaling which's able to convert and process the interlaced video to be displayed on progressive panels. The On Screen Display (OSD) window provides overlay of a control menu, text, or caption on the output display. It's built-in OSD generator with 2K Bytes programmable RAM fonts and also supports optional external OSD. AL260 is built-in 3-channel DAC for non-interlaced analog output and also supports 24bit digital output. It's housed with 208-pin QFP. (c)2002,2003-Copyright by AverLogic Technologies, Corp. Version B1.0 5 AL260 2. Function Block Diagram 3. Features 3.1 General Features Support Digital YUV input and Non-interlaced RGB/YPbPr Analog and Digital outputs Film Detection with Inverse 3:2/2:2 Pull Down Advanced De-interlacing with Motion Compensation AverLogic's Proprietary Cubic Scaling Algorithm for Scaling Up and Down Built-in 2K Bytes OSD RAM and support External OSD Font ROM Available in 208-pin PQFP 2.5V Core and 3.3V I/O power supplies with 5V input tolerant (c)2002,2003-Copyright by AverLogic Technologies, Corp. Version B1.0 6 AL260 3.2 Feature Description: Input Interface NTSC/PAL support Video interface ITU-R 601/656(8/16bit), YUV422 support Output Interface Output resolution up to 1280x1024 @60Hz Analog non-interlaced RGB/YPbPr output supported SDRAM Interface Support maximum 32bit bus width SDRAM interface, two SDRAMs configuration up to 125 MHz supported De-interlacing and Scan Rate Conversion De-Interlacing for Interlaced Video Input Motion Compensation De-interlacing with Spatial and Temporal Filtering support Film Detection with Inverse 3:2 & 2:2 pull down Frame Rate Conversion(FRC) from 50Hz up to 120Hz Scaling Engine and Video Processing Independent Scale Up and Down in both Horizontal and Vertical direction with 4-line, high precision interpolation Digital Brightness/Contrast/Saturation Control Keystone Correction for Front-Projection Systems Sharpness Control Built-in LUT for Gamma Correction and Color Adjustment Dithering Logic for Color Depth Enhancement I2C or Parallel Port Registers Access Registers can be accessed by serial I2C port or 8 bit parallel port for high speed registers data update On Screen Display (OSD) 2K Bytes Internal OSD RAM for fine bitmaps and text font (c)2002,2003-Copyright by AverLogic Technologies, Corp. Version B1.0 7 AL260 Dual internal OSD windows support with Alpha Blending/Transparency effect Support up to 64K Bytes External ROM for Font or Bitmap data In ROM mode, Internal OSD RAM supports 1.5K Bytes for Context RAM, 0.5K Bytes for Pre-fetch RAM Pre-fetch RAM supports different speed types of Font ROMs (EE-PROM, PROM or Mask-ROM) Other Features Primary input stream VBI pass through support Frame capture Mirroring support in Horizontal or Vertical direction NTSC/PAL Video Input Auto-Detection support Power Saving support Slave mode support Operating Power 2.5V core and 3.3V I/O power supplies with 5V input tolerant Package 208-pin PQFP 4 Applications LCD TV DTV & Front Projection/Rear Projection/Progressive Scan TVs TV to PC Monitor Format/Scan Rate Converter Video Enhancer/TV Tuner box (c)2002,2003-Copyright by AverLogic Technologies, Corp. Version B1.0 8 AL260 5 Application Example SDRAM 1M X 16bit SDRAM 1M X 16bit RGB/YPbPr Analog Output Audio Processor Analog Video (S-Video Or CVBS) Video Decoder 16/8 bit YUV AverLogic AL260 DVI Tx. PanelLink Digital Output LVDS Tx. MCU 64K MTP/OTP OSD Font ROM SVGA/XGA LCD Panel (c)2002,2003-Copyright by AverLogic Technologies, Corp. Version B1.0 9 6 Pin-Out Diagram PQFP-208 Package: (c)2002,2003-Copyright by AverLogic Technologies, Corp. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 VDD25 VSS25 AVDD33 AVSS25 AVDD25 VREFOUT VREFIN COMP RSET AVSS33R AVDD33R IOR AVSS33G AVDD33G IOG AVSS33B AVDD33B IOB VSS25 VDD25 AVSS33 VSS25 VDD25 VOUT4 VOUT3 VOUT2 VOUT1 VOUT0 MADDR10 MADDR9 MADDR8 MADDR7 MADDR6 VSS33 MADDR5 MADDR4 MADDR3 MADDR2 MADDR1 MADDR0 VDD25 PMXIN VSS33 MDATA31 MDATA30 MDATA29 MDATA28 MDATA27 MDATA26 MDATA25 MDATA24 VDD33 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 VDD33 P1VDD25 P1VSS25 P1AVSS25 P1AVDD25 P1VSS25 P1VDD25 P2VDD25 P2VSS25 P2AVSS25 P2AVDD25 P2VDD25 P2VSS25 MXOUT MXIN RDATA0 RDATA1 RDATA2 RDATA3 RDATA4 RDATA5 RDATA6 VSS33 RDATA7 VIN0 VIN1 VIN2 VIN3 VDD33 VIN4 VIN5 VIN6 VIN7 VDD25 VCLK VSS25 VHREF VHS VVS VIN8 VIN9 VDD25 VIN10 VIN11 VIN12 VIN13 VSS25 VIN14 VIN15 HOST_DB0 HOST_DB1 VSS33 Version B1.0 AL260 10 AL260 7 Pin Definition and Description 7.1 Input Format Table of AL260: VIN No. VIDEO 15~8 Y 7~0 CbCr YCbCr The pin-out definitions are described as follows: Pin Name Input Interface VIN [15:14], [13:10], [9:8] VIN [7:4], [3:0] VCLK VHREFF VHS VVS 33-30, 28-25 35 37 38 39 I I I I 49-48, 46-43, 41-40 I Video Input Bus Bit 7-0, upper 8 bits of ITU-R 601 16bit data bus OR Video Input Bus Bit 7-0 of ITU-R 656 8bit Reference Clock of Video Port HDE of Video Port HSYNC of Video Port VSYNC of Video Port I Video Input Bus Bit 15-8, lower 8 bits of ITU-R 601 16bit data bus Pin Number I/O type Description OSD ROM Interface RDATA [6:0], [7] RA [15:0] 203-188 22-16, 24 O ROM Address Bus Bit 15-0 I ROM Data Bus Bit 7-0 DAC Output Interface AVDD33 AVSS33 AVDD25 AVSS25 AVDD33R 154 136 152 153 146 AP AG AP AG AP 3.3v Analog Power for DAC Analog GND for DAC 2.5V Analog Power for DAC Analog GND for DAC 3.3 V Analog Power for Channel R (c)2002,2003-Copyright by AverLogic Technologies, Corp. Version B1.0 11 AL260 Pin Name AVSS33R AVDD33G AVSS33G AVDD33B AVSS33B DVDD25 DVSS25 IOR IOG IOB RSET COMP VREFIN VREFOUT Pin Number 147 143 144 140 141 137 138 145 142 139 148 149 150 151 I/O type AG AP AG AP AG AP AG O O O I I I O Description Analog GND for Channel R 3.3 V Analog Power for Channel G Analog GND for Channel G 3.3 V Analog Power for Channel B Analog GND for Channel B 2.5V Digital Power for DAC Digital GND for DAC Channel R Current Output Channel G Current Output Channel B Current Output Full-Scale Adjust Resister Compensation Pin Voltage Reference Input Voltage Reference Output Digital Output Panel Interface VOUT [23:16], [15:5], [4:0] SCLK PDSDEN PHS PVS OXIN SDRAM Interface MDATA [31:24], [23-12], [11:0] MADDR [10:6], [5:0] 128-124, 122-117 113-106, 103-92, 83-72 I/O SDRAM Address Bit 10-0 I/O SDRAM Data Bus Bit 31-0 185-178, 168-158, 133-129 170 172 173 174 176 O O I I I Display Pixel Clock Display Data Enable HSYNC Input for Slave Mode VSYNC Input for Slave Mode Reference Clock for Display Device O Digital Video Output Bit 23-0 (c)2002,2003-Copyright by AverLogic Technologies, Corp. Version B1.0 12 AL260 Pin Name PMXIN BA[1:0] RASB CASB WEB CLK Host Interface HOST_DB [7:2], [1:0] HOST_WRB HOST_RDB HOST_DENB HOST_MEMB HOST_RDYB IREQ SDA SCL I2C_EN INTB PLL Interface MXIN MXOUT P1VDD25 P1VSS25 P1AVDD25 P1AVSS25 P2VDD25 P2VSS25 P2AVDD25 P2AVSS25 Others 15 14 2,7 3,6 5 4 8,12 9,13 11 10 I O DP DG AP AG DP DG AP AG Crystal Input (14.31818MHz) Crystal Output 2.5V Pad Ring Power for PLL1 Pad Ring GND for PLL1 Analog Power for PLL1 Analog GND for PLL1 2.5V Pad Ring Power for PLL2 Pad Ring GND for PLL2 Analog Power for PLL2 Analog GND for PLL2 59-54, 51-50 63 64 65 69 70 71 205 204 186 206 I I I I O O I/O I I O Reference Clock Read/Write Strobe Data Cycle Memory Cycle Read Data Ready Output Interrupt Output Data Bit for Serial Bus Clock Bit for Serial Bus I2C Enable Interrupt for Serial Protocol I/O Host Bus Bit 7-0 Pin Number 115 91-90 89 88 87 85 I/O type I O O O O O Description SDRAM Read Data Input Sampling Clock SDRAM Bank Address Bit 0-1 SDRAM Row Address Strobe SDRAM Column Address Strobe SDRAM Write Enable SDRAM reference Clock (c)2002,2003-Copyright by AverLogic Technologies, Corp. Version B1.0 13 AL260 Pin Name RSTB NC Pin Number 207 61, 67 I/O type I Reset No Connection Description DIGITAL POWER / GROUND VDD25 34, 42, 62, 86, 116, 134, 156, 177 VSS25 36, 47, 60, 68, 84, 135, 155, 171, 187 VDD33 1, 29, 53, 66, 105, 169, 208 VSS33 23, 52, 104, 114, 123, 157, 175 DG Digital Ground 3.3V DP Digital Power 3.3V DG Digital Ground 2.5V DP Digital Power 2.5V Note: For I/O type, "I", "O", "AP", "AG", "DP", and "DG" stand for "Input", "Output", "Analog Power", "Analog Ground", "Digital Power", and "Digital Ground" respectively. (c)2002,2003-Copyright by AverLogic Technologies, Corp. Version B1.0 14 AL260 8 General Function Description 8.1 Function Blocks AL260 provide a fully programmable structure allowing video stream process more flexible. The AL260 data process is executed by parsing in the modules such as capture, down scale, memory, up scale and mixer. In each module, data will be manipulated corresponding to the setting of registers. Due to the lack of the number of registers, some registers require banking to other page for access. There are 4 group registers, base control registers, capture control registers, memory control registers and display control registers. The value of base register 0eh determines which group of registers is taken effect. If register 0eh is programmed to value 00, the group of base control registers is chosen; and the register 0eh with value 01 is for capture register group, value 02 is for memory register group and value 03 is for display register group. The register 0eh must be set to corresponding value before that group of register can be accessed. Register Group ID 00 <1:0> 01 10 11 Group register Description Access only base control registers Access capture and base control registers Access memory and base control registers Access display and base control registers Symbol BAS# CAP# MEM# DIS# Example BAS#16 CAP#20 MEM#32 DIS#61 0Eh 8.2 VIU (Video Input Unit) AL260 accepts 16/8bit YUV 4:2:2 (NTSC/PAL) video data stream with ITU-R-656/601 standards. Applying AverLogic Proprietary Scaling algorithm, the video stream can be scaled down to accommodate required output resolutions with high quality scaling effect. The high quality scaling engine also ensures full screen output display. 8.2.1 Input Data Format The AL260 is an integrated video processor that automatically detects and converts multiple video formats. The Index and Base registers provide user an expansion of the (c)2002,2003-Copyright by AverLogic Technologies, Corp. Version B1.0 15 AL260 control registers, which implements easy control of the input and the desired output format. The Base registers control the input type and target format. The AL260 accepts two data formats: 8-bit ITU-R BT.656 (CCIR656) and 16-bit CCIR601 422. The clock and sync signal pins separate for RGB or YUV while the YUV data share the same pins as RGB data. For detailed applications, please refer to AL260 Application Notes. 8.2.2 Video Capture and Down Scale Engine The AL260 has a high-quality scaling engine performing proprietary scaling operations independently in both Horizontal and Vertical direction with 4-line, high precision interpolation. (c)2002,2003-Copyright by AverLogic Technologies, Corp. Version B1.0 16 AL260 8.2.3 Automatic Positioning Registers The AL260 can detect and report input capture timing for Auto-adjustment function. It detects the starting and ending positions of active video in both direction (Horizontal and Vertical) and ensures the output fit properly into the display region. The data threshold value defines the sensibility of valid data. The capture data will be sampled and qualified base upon the value of data threshold, so that it can determine the starting point and ending point of an active line or an active frame. 8.2.4 PLL Programming for Memory and Display Clock AL260 embedded 2 independent 200MHz PLL-Based Clock Generator. One is used to generate SDRAM clock, the other is for output clock. They are all reference input clock from XIN (generally 14.318MHZ). There are 3 operation modes in defined in PLL register: Power Down Mode, Bypass Mode and Normal Mode. Power Down Mode forces FOUT to low and PLL in low power consumption state (<10uW). Bypass Mode provides FOUT with the same frequency as FIN. Normal Mode synthesizes FOUT by programming suitable divider values. It needs a Tready time (Pull_in Time + Locking Time) for PLL to re-lock the FIN clock when PLL wakes up from Power Mode to Normal Mode. In general, it should be reserved a Tread time for re-locking when PLL is changed to Normal Mode from Power Mode or Bypass Mode, or when any divider setting is changed. 8.3 MIU (Memory Interface Unit) MIU supports SDRAM 32bit bus width interface. AL260 supports various SDRAM configurations, such as 512Kx16, 2ea. It uses sequential Burst mode to control SDRAM memory that operates at minimum 120MHz of clock frequency. For detailed operation of SDRAM, please reference memory specifications. 8.3.1 DRAM Bandwidth Consideration The AL260 uses external DRAMS for the purpose of frame rate conversion between the (c)2002,2003-Copyright by AverLogic Technologies, Corp. Version B1.0 17 AL260 input video and the output video device. The frame rate conversion for video is done by double buffering. 8.3.2 DRAM Input/Output Windows The proceeding diagrams will describe the DRAM input control. The DRAM input data size depends on the horizontal capture destination size. After the input data size has been defined, the memory address of input data can be determined by the register DRAM input stride. The DRAM input stride can be programmed to provide extra memory space for input data. 8.3 VPU (Video Processing Unit) AL260 identifies video input sources including Progressive Film (24/25 fames/sec) and Interlaced Video (50/60 fields/sec) and selects appropriate de-interlacing algorithm for video enhancement. VPU supports Film Detection with Inverse 3:2 or 2:2 Pull Down and AverLogic Proprietary De-interlacing. When AL260 detects the video source as Film, then (c)2002,2003-Copyright by AverLogic Technologies, Corp. Version B1.0 18 AL260 progressive scan frames will be reassembled and output twice input rate such as 50/60 frame/sec. Otherwise, it will be taken as Interlaced Video Source, and processed by using De-interlacing to reduce video artifacts. The scaling engine offers Scale-Up effect by applying Cubic Scaling Algorithm. It supports independent Scale-Up in both Horizontal and Vertical direction with 4-line, high precision interpolation. AL260 also offers Digital Contrast, Brightness, and Saturation for Color adjustment. It can be adjusted in YUV data. The Sharpness Control provides good effect for image enhancement. It also provides Keystone function for Projector application. 8.4.1 Video De-Interlaced with Film Detection and Motion Adaptive Video Processing unit equips a high quality de-interlacing algorithm to optimize the output progressive scan frame by recovering film sequence and compensating motion effect during the de-interlacing process. The motion estimation can evaluate both Y/C data or Y data by setting register. In Motion compensation process, the sensitivity of the data estimation can be adjusted by register for Lumina and Chroma threshold. In film video, such as DVD movie, some duplicate fields are inserted into the interlaced video stream. Original film sequence detection and recovery can produce a smooth progressive scan frame transition after de-interlaced. 8.4.2 Up Scale Engine The Up Scale Engine can scale up Primary Stream to higher resolution in high quality for output display. The AL260 adapts FIR scaling engine that can do horizontal and vertical up scale independently. The primary stream picture can be either down scale to smaller size of picture or up scale to larger size of picture from original capture (input) picture for output, but it can not do both up and down scale process at the same time. Consider to capture full picture of input data if the output resolution of primary stream picture is going to be enlarged. Following block diagram illustrates the define registers of source primary stream window and destination up scale window. (c)2002,2003-Copyright by AverLogic Technologies, Corp. Version B1.0 19 AL260 8.4.3 Keystone Up Scale Engine The AL260 can scale up the image in dynamic ratio which is good for LCD projector image correction. The projected images from the LCD projector sometimes show as Figure due to the misalignment or cheap optics. The AL260 can up scale picture in dynamic ratios which are loaded from pre-stored at internal FIFO buffers. The keystone is designed to compensate the distortions, such as figures following. 8.4 VOU (Video Output Unit) Two independent On-Screen-Display (OSD) windows provide overlay for a control menu, text, or caption on the output display. The AL260's OSD is very flexible in the way that the font, size, and display location are all programmable. The internal 2K byte SRAM provides storage for the OSD information. The OSD can be operated with only this (c)2002,2003-Copyright by AverLogic Technologies, Corp. Version B1.0 20 AL260 internal SRAM or with an external ROM to store font tables or even larger bitmaps. Builtin 8bit Programmable Gamma Look-Up Table for each input color channel for Gamma Correction. It may be used for RGB Contrast, Brightness and Color Temperature adjustments. Dithering is performed to retain color resolution for LCD panels that support 18-bit color depths. AL260 provides Digital video output interface that can be directly connected to 24bit TFT LCD Panel or DVI/LVDS Transmitters. It also provides Analog video output which can support up to SXGA resolution. (c)2002,2003-Copyright by AverLogic Technologies, Corp. Version B1.0 21 AL260 8.5.1 OSD Two independent On-Screen-Display (OSD) windows provide overlay for a control menu, text, or caption on the output display. The AL260's OSD is very flexible in the way that the font, size, and display location are all programmable. The internal 2K byte SRAM provides storage for the OSD information. The OSD can be operated with only this internal SRAM or with an external ROM to store font tables or even larger bitmaps. Regarding the detailed usage, please refer to AL260's OSD Application Note. 8.5.2 LUT (Look up table for Gamma Correction and Color Enhancement) Because of the different characteristics of TV's and PC monitors, direct color space conversion from TV to PC may not show the same color that the human eye sees from the original video on the TV. The contrast may not be sufficient, and the hue may not be accurate, so to resolve these issues the AL260 has a gamma correction internal LUT implemented. The AL260 provides programmable registers for implementing the LUT. The directly converted colors are sent to the LUT that then sends out the mapped, corrected colors. The user can program the LUT based on his/her own experiments on specific types of monitors. The typical input-output mapping curve is usually somewhat like the following: Output Corrected Conversion Direct Conversion Input Figure 11 LUT Mapping (c)2002,2003-Copyright by AverLogic Technologies, Corp. Version B1.0 22 AL260 8.5.3 Dithering The AverLogic offers dithering technique that simulates display of colors that are not in the current color space of a particular image. The Dithering logic provides additional color depth enhancement to retain color resolution for LCD panels that support 18-bit color depth. 8.5 BIU (Bus Interface Unit) It supports I2C serial and proprietary parallel programming interfaces. I2C serial interface requires two wires to access while the proprietary parallel interface needs 11 wires. The communication speed of proprietary parallel interface is much faster than I2C serial interface. Regarding to the detailed usage, please refer to AL260's General Application Note. (c)2002,2003-Copyright by AverLogic Technologies, Corp. Version B1.0 23 AL260 9 Register Definition Registers are provided to setup AL260. These registers can be programmed via host interface. The host interface protocol is illustrated in "Host Interface" paragraph. The application notes will describe more detailed settings about these registers. Upon request, AverLogic will provide the sample code or tool of host interface control software. 9.1 Register Set Register Name Base Control Group Registers COMPANYID INTRMASK INTRSTATUS CAPCTRL DISCTRL1 DISCTRL2 POLARITYCTRL OTIMECTRL GROUPACCESS INSRCFORMAT INPUTCTRL HREFDLY CAPCTRL1 CAPCTRL2 MEMACCR INVMSB PLLSETR MPLLNF MPLLNRO OPLLNF OPLLNRO 00h 02h 03h 06h 07h 08h 09h 0Ah 0Eh 11h 12h 13h 14h 16h 17h 18h 1Bh 1Ch 1Dh 1Eh 1Fh R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 46h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h Company ID Interrupt Mask Interrupt Vector and Mode Capture Data Control Display Data Control 1 Display Data Control 2 Display Polarity Control Display Timing Control Group Access ID Input Video Source Format Input Control Horizontal Reference Delay Capture control 1 Capture control 2 Memory Access Control Inverted MSB of Capture Data Format PLL Setting for Memory and Display LSB of NF Value for Memory PLL MSB of NF/NR/NO Value for Memory PLL LSB of NF Value for Display PLL MSB of NF/NR/NO Value for Display PLL Address R/W Default Function Capture Control Group Registers(Accessible when BAS#0E = 01h) Capture Timing CAPHSTART 21h & 20h R/W 00h Horizontal Capture Start (c)2002,2003-Copyright by AverLogic Technologies, Corp. Version B1.0 24 AL260 Register Name CAPHSRCSIZE CAPHDESTSIZE CAVSTART CAPVSRCSIZE CAPVDESTSIZE INTERLACECTRL HDNRATIO VDNRATIO VBI Input Timing VBIVSTART VBIVEND VBIHSTART VBIHSIZE ITU-656 Detection 656HSTART 656HEND 656VSTART 656VEND Position Detection POSDATATH POSHDESTART POSHDEEND POSVDESTART POSVDEEND Mode Detection CAPHTOTALCNT CAPVTOTALCNT DBUFFLAGNUML DBUFFLAGNUMH TUNEINCLK 63h & 62h 65h & 64h 70h 72h 73h R R R/W R/W R/W 00h 00h 00h Horizontal Capture Total Counter Vertical Capture Total Counter Double Buffer Flag Number LSB Double Buffer Flag Number MSB Tune Input Clock Timing 50h 53h & 52h 55h & 54h 57h & 56h 59h & 58h R/W R R R R 00h Data Threshold for Position Detection Horizontal Capture Active Start Horizontal Capture Active End Vertical Capture Active Start Vertical Capture Active End 38h 39h 3Ah 3Bh R/W R/W R/W R/W 20h A0h 02h 04h ITU656 data Horizontal sync start ITU656 data Horizontal sync end ITU656 data Vertical sync start ITU656 data Vertical sync end 34h 35h 36h 37h R/W R/W R/W R/W 00h 00h 00h 00h VBI Vertical Capture Start VBI Vertical Capture End VBI Horizontal Capture Start VBI Horizontal Capture Size Address 23h & 22h 25h & 24h 27h & 26h 29h & 28h 2Bh & 2Ah 2Eh 31h & 30h 33h & 32h R/W R/W R/W R/W R/W R/W R/W R/W R/W Default 00h 00h 00h 00h 00h 00h 00h 00h Function Horizontal Capture Source Size Horizontal Capture Destination Size Vertical Capture Start Vertical Capture Source Size Vertical Capture Destination Size Interlace Control Horizontal Scale Down Ratio Vertical Scale Down Ratio Memory Control Group Registers(Accessible when reg.0Eh = 02h) DRAM Control (c)2002,2003-Copyright by AverLogic Technologies, Corp. Version B1.0 25 AL260 Register Name DRAMACCESSCTRL DRAMWRITE OUTFIFOCTRL INFIFOCTRL DRAMMINREFRESH DRAMCTRL DRAMRADDR XYMIRRORIN XYMIRROROUT SKIPMODE DRAM Input Window Control DRAMSTART DRAMSTRIDE DRAMISIZE DRAM Window Copy Control WCSRCSTART GSDRAMINPUTSTRIDE GSDRAMINPUTSIZE WCSTRIDE WCDESTSTART DASTART WCSIZE WCLINETOTAL DRAM Output Window Control DRAMSTART DRAMSTRIDE DRAMSIZE VBISTART FRONTMD TUNEMCLK TUNEPMCLK DRAM Data Port 47h 48h 49h 4Fh ~ 4Dh 50h 51h 52h R/W R/W R/W R/W R/W R/W R/W 00h 00h 00h 00h 00h 00h 00h DRAM Output Start DRAM Output Stride DRAM Output Size VBI Starting Address Front Motion Detect Control Tune Memory Write Clock Timing Tune Memory Read Clock Timing 3Bh ~ 39h 3Ch 3Dh 3Eh 41h ~ 3Fh 44h ~ 42h 45h 46h R/W R/W R/W R/W R/W R/W R/W R/W 00h 00h 00h 00h 00h 00h 00h 00h Window Copy Source Start Window Copy Source Stride Window Copy HSize Direct Write Stride Window Copy Destination Start Direct Read/Write Address Window Copy Size Window Copy Line Total 33h 34h 35h R/W R/W R/W 10h 00h 00h DRAM Input Start DRAM Input Stride DRAM Input Size Address 20h 21h 22h 23h 28h 2Ah & 29h 2Dh ~ 2Bh 30h 31h 32h R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Default 00h 00h 00h 00h 00h 00h 00h 00h 00h 10h Function DRAM Access control DRAM Write Output FIFO Control Input FIFO Control DRAM Minimum Refresh DRAM Control Register DRAM Read Address XY Mirror Input XY Mirror Output Skip Mode (c)2002,2003-Copyright by AverLogic Technologies, Corp. Version B1.0 26 AL260 Register Name READSTATUS BYTE0 BYTE1 BYTE2 BYTE3 BYTE4 BYTE5 Address 60h 61h 62h 63h 64h 65h 66h R/W R R/W R/W R/W R/W R/W R/W 00h 00h 00h 00h 00h 00h Default Read Status Byte 0 Byte 1 Byte 2 Byte 3 Byte 4 Byte 5 Function Display Control Group Registers (Accessible when reg.0Eh = 03h) Display Timing DISHTOTAL DISHSEND DISHDESTART DISHDEEND DISVTOTAL DISVSEND DISVDESTART DISVDEEND Window Output Timing DISHDESTART DISHDEEND DISVDESTART DISVDEEND Zoom In Control Registers DISHSRCSIZE DISHDESTSIZE DISVSRCSIZE DISVDESTSIZE ZOOMFCTRL HUPRATIO DELTAHUPRATIO VUPRATIO HPHASE 41h & 40h 43h & 42h 45h & 44h 47h & 46h 48h 4Bh & 4Ah 4Bh & 4Ah 4Dh & 4Ch 4Fh & 4Eh R/W R/W R/W R/W R/W R/W R/W R/W R/W 00h 00h 00h 00h 00h 00h 00h 00h 00h Horizontal Display Source Size Horizontal Display Destination Size Vertical Display Source Size Vertical Display Destination Size Zoom In Filter Control Horizontal Scale Up Ratio Delta Horizontal Scale Up Ratio Vertical Scale Up Ratio Horizontal Scale Up Initial Phase 31h & 30h 33h & 32h 35h & 34h 37h & 36h R/W R/W R/W R/W 00h 00h 00h 00h Horizontal Display Start Horizontal Display End Vertical Display Start Vertical Display End 21h ~ 20h 23h & 22h 25h & 24h 27h & 26h 29h & 28h 2Bh & 2Ah 2Dh & 2Ch 2Fh & 2Eh R/W R/W R/W R/W R/W R/W R/W R/W 00h 00h 00h 00h 00h 00h 00h 00h Display Horizontal Total Display Horizontal Sync Horizontal Display Start Horizontal Display End Display Vertical Total Display Vertical Sync Vertical Display Start Vertical Display End (c)2002,2003-Copyright by AverLogic Technologies, Corp. Version B1.0 27 AL260 Register Name VPHASE OUTPUTMODE LUTINDEX LUTRED LUTGREEN LUTBLUE LUTCOLOR PATTERNGEN OSD Color Registers OSDRAMWADDR OSDRAMWDATA COLOR0RED COLOR0GREEN COLOR0RED COLOR1RED COLOR1GREEN COLOR1BLUE COLOR2RED COLOR2GREEN COLOR2BLUE COLOR3RED COLOR3GREEN COLOR3BLUE COLOR4RED COLOR0GREEN COLOR4BLUE COLOR5RED COLOR5GREEN COLOR5BLUE COLOR6RED COLOR6GREEN COLOR6BLUE 59h & 58h 5Ah 60h 61h 62h 63h 64h 65h 66h 67h 68h 69h 6Ah 6Bh 6Ch 6Dh 6Eh 6Fh 70h 71h 72h 73h 74h R/W W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h OSD Write Address OSD Write Data Port Color 0 Red Color 0 Green Color 0 Blue Color 1 Red Color 1 Green Color 1 Blue Color 2 Red Color 2 Green Color 2 Blue Color 3 Red Color 3 Green Color 3 Blue Color 4 Red Color 4 Green Color 4 Blue Color 5 Red Color 5 Green Color 5 Blue Color 6 Red Color 6 Green Color 6 Blue Address 51h & 50h 54h 55h 5Ch 5Dh 5Eh 5Fh 56h R/W R/W R/W R/W R/W R/W R/W R/W R/W Default 00h 00h 00h 00h 00h 00h 00h 00h Function Vertical Scale Up Initial Phase Output Mode LUT Write Index LUT Red Color LSB LUT Green Color LSB LUT Blue Color LSB LUT Color MSB and Read/Write Trigger Pattern Generator and GPO (c)2002,2003-Copyright by AverLogic Technologies, Corp. Version B1.0 28 AL260 Register Name COLOR7RED COLOR7GREEN COLOR7BLUE OSD Control Registers OSDCOLORSEL BLINKTIME OSDMODE FOREOP FOREOP FADEALPHA OSD1 Registers OSDCONTROL1 ROMSTARTADDR1 FONTADDRUNIT1 OSDHSTART1 OSDVSTART1 RAMADDRST1 RAMSTRIDE1 BMAPHSIZE1 BMAPHTOTAL1 BMAPVSIZE1 BMAPVTOTAL1 ICONHTOTAL1 ICONVTOTAL1 FONTLINESIZE1 OSD2 Registers OSDCONTROL2 ROMSTARTADDR2 FONTADDRUNIT2 OSDHSTART2 OSDVSTART1 RAMADDRST2 88h 89h 8Ah A0h A1h A2h R/W R/W R/W R/W R/W R/W 00h 00h 00h 00h 00h 00h OSD2 Control OSD2 ROM Start Address OSD2 Font Address Unit OSD2 Horizontal Start OSD2 Vertical Start OSD2 RAM Start Address 84h 85h 86h 90h 91h 92h 8Bh & 93h 95h & 94h 97h & 96h 99h & 98h 9Bh & 9Ah 9Ch 9Dh AEh R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h OSD1 Control OSD1 ROM Start Address OSD1 Font Address Unit OSD1 Horizontal Start OSD1 Vertical Start OSD1 RAM Start Address OSD1 RAM Horizontal Stride OSD1 Bitmap Horizontal Size OSD1 Bitmap Horizontal Total Pixels OSD1 Bitmap Vertical Size OSD1 Bitmap Vertical total Lines OSD1 Icon Horizontal Total OSD1 Icon Vertical Total OSD1 Font Line Size 78h 79h 80h 81h 83h 82h R/W R/W R/W R/W R/W R/W 00h 00h 00h 00h 00h 00h OSD Color Select OSD Blink Timer OSD Modes Logic Operation 1 Logic Operation 2 Fading Alpha Value Address 75h 76h 77h R/W R/W R/W R/W Default 00h 00h 00h Color 7 Red Color 7 Green Color 7 Blue Function (c)2002,2003-Copyright by AverLogic Technologies, Corp. Version B1.0 29 AL260 Register Name RAMSTRIDE2 BMAPHSIZE2 BMAPHTOTAL2 BMAPVSIZE2 BMAPVTOTAL2L ICONHTOTAL2 ICONVTOTAL2 FONTLINESIZE2 Desktop Color Registers DESKR DESKG DESKB B3h B4h B5h R/W R/W R/W 00h 00h 00h Desktop Color Component Red Desktop Color Component Green Desktop Color Component Blue Address 8Ch & A3h A5h & A4h A7h & A6h A9h & A8h ABh & AAh ACh ADh AFh R/W R/W R/W R/W R/W R/W R/W R/W R/W Default 00h 00h 00h 00h 00h 00h 00h 00h Function OSD2 RAM Horizontal Stride OSD2 Bitmap Horizontal Size OSD2 Bitmap Horizontal Total Pixels OSD2 Bitmap Vertical Size OSD2 Bitmap Vertical Total Lines OSD2 Icon Horizontal Total OSD2 Icon Vertical Total OSD2 Font Line Size Film Detection/ Motion Compensation Registers MOTIONCNTTH LUMATH CHROMATH MCCTRL FILMCTRL PHASECTRL MVCNT C5h & C4h C6h C7h C8h C9h CAh CFh & CEh R/W R/W R/W R/W R/W R/W R 00h 00h 00h 00h 00h 00h 00h Motion Counter Threshold Lumina(Y) Threshold Chroma(C) Threshold De-interlacing Control Register Film Detection Control Register Phase Detection Control Register Motion Pixel Numbers Keystone/Sharpness Registers SHPKEYCTRL KEYADDR Tri-Level Sync Registers TRISYNCA TRISYNCB TRISYNCD1 TRISYNCD2 TRISYNCBLANK TRISYNCLEVEL Display Parameter Registers DISTUNEHS C2h R/W Tune Display Horizontal Sync Phase D0h D1h D2h D3h D4h D7h W W W W W W 00h 00h 00h 00h 00h 00h Tri-Level Sync Parameter Period a Tri-Level Sync Parameter Period b Tri-Level Sync Parameter Delta 1 Tri-Level Sync Parameter Delta 2 Tri-Level Sync Parameter Period Blank Tri-Level Sync Level CBh C1h & C0h R/W R/W 00h 00h Sharpness/Keystone Control Register Keystone Parameters Address (c)2002,2003-Copyright by AverLogic Technologies, Corp. Version B1.0 30 AL260 Register Name DISTUNESCLK PHASECTRL DISHTOTAL DISVTOTAL PHASECNT DISADJEN BRIGHTNESS CONTRAST SATURATION Address CCh CAh D8h & D7h DAh & D9h DCh & DBh F0h F1h F2h F3h R/W R/W R/W R R R R/W R/W R/W R/W 00h 80h 40h 40h Default Function Tune Display Pixel Clock Phase Phase Detection Control Register Display Horizontal Total Counter Display Vertical Total Counter Phase Counter Enable Brightness/Contrast/Saturation Brightness Level Contrast Level Saturation Level (c)2002,2003-Copyright by AverLogic Technologies, Corp. Version B1.0 31 AL260 9.2 Register Description Base Control Group Registers INDEX (HEX) 00 Register Description Register Name BITS Function Description Company ID (R) [COMPANYID] CompanyID <7:0> Company ID (46h) 02 Interrupt Mask (R/W) [INTRMASK] DVsyncIntMask <0> Display VSYNC interrupt mask 0 1 CAPVsyncIntMask <1> 0 1 Reserved VBlMask <2> <3> Mask interrupt issued by VSYNC of display Interrupt issued when display VSYNC is activated Mask interrupt issued by VSYNC Interrupt issued when VSYNC is activated Capture VSYNC interrupt mask Reserved Display vertical blank interrupt mask 0 1 Mask interrupt issued by display vertical blank Interrupt issued by display vertical blank Mask interrupt issued by film detection Interrupt issued when HW film detected Mask interrupt issued by FIFO full for directly write to SDRAM 1 Interrupt issued by FIFO full for directly write to SDRAM Mask interrupt issued by window copy Interrupt issued by window copy Mask interrupt issued by FIFO index of arbiter Interrupt issued when FIFO is full FilmDetMask <4> H/W Film detected finished interrupt mask 0 1 FullDetMask <5> FIFO full for directly memory write Interrupt Mask 0 WCopyEndMask <6> Window copy finished interrupt mask 0 1 FIFOFullMask <7> Arbiter FIFO full interrupt mask 0 1 (c)2002,2003-Copyright by AverLogic Technologies, Corp. Version B1.0 32 AL260 03 Interrupt Vector and Mode (R)(W) [INTRSTATUS] DVsyncInt (R) CAPVsyncInt (R) Reserved VBlInt (R) FilmDet (R) FullDet (R) WCopyEnd (R) FIFOFull (R) IntMode(W) <0> <1> <2> <3> <4> <5> <6> <7> <0> Display VSYNC interrupt Capture VSYNC interrupt Reserved Display vertical blank interrupt H/W Film detected finished interrupt FIFO full for directly memory write interrupt Window copy finished interrupt Arbiter FIFO full interrupt 0 1 <1> 0 1 <7:2> Trigger mode Level mode High active Low active Reserved 04~05: Reserved 06 Capture Data Control (R/W) [CAPCTRL] CapVScaleDn <0> Capture vertical scale down enable 0 1 Reserved SoGo Reserved GO <4:1> <5> <6> <7> Disable Enable Tie to "0000" Display timing strobe by capture VSYNC Tie to 1 Capture timing enable 0 1 Disable Enable 07 Display Data Control 1 (R/W) [DISCTRL1] Reserved CscEn <2:0> <3> Tie to "011" Capture data color space conversion 0 1 Disable color space converter Enable color space converter (c)2002,2003-Copyright by AverLogic Technologies, Corp. Version B1.0 33 AL260 Reserved 08 <7:4> Reserved Display Data Control 2 (R/W) [DISCTRL2] UVFlip2Path <0> U/V flip in display data path 0 1 UVFlip2Mem <1> 0 1 Reserved YPbPrEn <2> <3> Disable Enable Disable Enable U/V flipped in capture data path Tie to "0" Color space conversion, refer to BAS#07<3> 0 1 YCbCr to RGB conversion YPbPr to RGB conversion Reserved 09 <7:4> Reserved Display Polarity Control (R/W) [POLARITYCTRL] OClkSel <0> Output clock source selection as display clock, refer to BAS#09<7> 0 1 ControlEn <1> Select OXIN1 as display clock Select OXIN2 as display clock Panel output data signals (clock, data, HSYNC, VSYNC and PDE) control enable 0 1 Disable output data signals to panel, all output data signals tie to low Enable panel output data signals Positive Negative Positive Negative Positive Negative HSyncPol <2> Output horizontal sync polarity 0 1 BlankPol <3> Output horizontal blank polarity 0 1 VSyncPol <4> Output vertical sync polarity 0 1 (c)2002,2003-Copyright by AverLogic Technologies, Corp. Version B1.0 34 AL260 InvertOdd <5> Invert odd field signal 0 1 CSyncOut <6> 0 1 OPLLSel <7> 0 1 0A Positive Negative Separate Composite From external pin (OXIN1/OXIN2) From PLL Composite sync out Display reference clock source, refer to BAS#09<0> Display Timing Control (R/W) [OTIMECTRL] WinDisable <0> Display window diable 0 1 Reserved SlaveMode <1> <2> Enable Disable Reserved Slave mode enable, refer to BAS#0A<3> 0 1 Output timing driven by internal registers Output timing driven by external device(capture or external display device) SlaveType <3> Slave mode type, refer to BAS#0A<2> 0 1 Output timing is driven by capture timing Output timing is driven by external display device XOR AND NXOR NAND RGB output YpbPr output RGB output YpbPr output CSYNCType <5:4> Compsit SYNC type 00 01 10 11 YPbPrAnalogOut <6> YPbPr analog output 0 1 YPbPrDigitalOut <7> YPbPr digital output 0 1 (c)2002,2003-Copyright by AverLogic Technologies, Corp. Version B1.0 35 AL260 0E Group Access ID (R/W) [GROUPACCESS] GroupAccessID <1:0> Group register access control 00 01 10 11 Reserved 11 <7:2> Access only Base control registers Access Capture and Base control registers Access Memory and Base control registers Access Display and Base control registers Reserved Input Video Source Format (R/W) [INSRCFORMAT] CapInFormat <1:0> Capture data input format 00 01 10 11 Reserved Reserved Reserved <5:2> <6> <7> Tie to 0 Reserved Reserved 16-bit 8-bit Reserved Reserved 12 Input Control (R/W) [INPUTCTRL] Reserved HsPol <2:0> <3> Tie to "000" Enable HS polarity detection 0 1 VsPol <4> 0 1 Reserved <7:5> Disable, when turn on auto position function Enable Disable, when turn on auto position function Enable Enable VS polarity detection Reserved 13 Horizontal Reference Delay (R/W) [HREFDLY] CapHRefDly Reserved <3:0> <7:4> Capture HRef delay Reserved 14 Capture control 1 (R/W) [CAPCTRL1] CapHScaleDn <0> Enable horizontal capture scale down (c)2002,2003-Copyright by AverLogic Technologies, Corp. Version B1.0 36 AL260 Reserved Cap656SyncSel <1> <2> Reserved Capture SYNC source when ITU656 input 0 1 CapSoftRef <3> 0 1 Reserved 16 <7:4> From external SYNC input pin From decoded ITU656 data From external HREF input pin Software programmable Capture HREF source Reserved Capture control 2 (R/W) [CAPCTRL2] Reserved InvOddField Reserved Cap444En <1:0> <2> <3> <4> Tie to "00" Invert internal detected capture odd field signal Reserved Input data format 0 1 Cap656En DEdgeEn Reserved <5> <6> <7> YPbPr input format YCbCr input format Enable input source is ITU656 format Double edge sampling for ITU656 input Reserved 17 Memory Access Control Register(R/W) [MEMACCR] MemWEn MemREn HostMode <0> <1> <2> Directly write enable Directly read enable Host data mode 0 1 Reserved DMAEn Reserved WCopyEn <3> <4> <5> <6> 2x16-bit per each host cycle 1x24-bit per each host cycle Tie to "1" Enable data output of directly memory Reserved Window copy enable 0 1 Disable window copy Enable window copy Memory clock from external PIN (XIN) MclkSel <7> Memory clock select 0 (c)2002,2003-Copyright by AverLogic Technologies, Corp. Version B1.0 37 AL260 1 18 Memory clock from internal PLL Inverted MSB of Capture Data Format (R/W) [INVMSB] InvBit7 InvBit15 InvBit23 Reserved <0> <1> <2> <7:3> Inverted bit 7 of input data Inverted bit 15 of input data Inverted bit 23 of input data Reserved Note: Please refer to General Application Note PLL Registers 1B PLL Setting Register for Memory and Display(R/W) [PLLSETR] OPLLPd <0> Power Down for Display PLL 0 1 OPLLVon <1> 0 1 OPLLBp <2> 0 1 OPLLOe <3> 0 1 MPLLPd <4> 0 1 MPLLVon <5> 0 1 MPLLBp <6> 0 1 MPLLOe <7> 0 PLL normal Operation PLL Power Down PLL normal Operation Reset the PLL NF & NR Divider PLL normal Operation Bypass the PLL & FOUT=FIN FOUT= Fck/NO FOUT=0 PLL normal Operation PLL Power Down PLL normal Operation Reset the PLL NF & NR Divider PLL normal Operation Bypass the PLL & FOUT=FIN FOUT= Fck/NO Reset for Display PLL Bypass Mode for Display PLL Output Control for Display PLL Power Down for Memory PLL Reset for Memory PLL Bypass Mode for Memory PLL Output control for memory PLL (c)2002,2003-Copyright by AverLogic Technologies, Corp. Version B1.0 38 AL260 1 FOUT=0 Note: FOUT = FIN * NF/(NR*NO) = FVCO/NO, here FVCO is between 80MHz and 190Mhz Here, FIN is input clock (example:14.31818MHz XTAL) NF/NR, and NO are refer to BAS#1C~1F definition 1C LSB of NF Value for Memory PLL(R/W) [MPLLNF] MPLLNF Note: NF is MPLLNF+2 1D MSB of NF/NR/NO Value for Memory PLL(R/W) [MPLLNRO] MPLLNR MPLLNO MPLLNF <4:0> <6:5> <7> MPLLNR<4:0> value for memory PLL MPLLNO<1:0> value for memory PLL MPLLNF<8> Value for memory PLL <7:0> MPLLNF<7:0> Value for memory PLL Note: NR is MPLLNR+2, NO is MPLLNO+1 1E LSB of NF Value for Display PLL(R/W) [OPLLNF] OPLLNF Note: NF is OPLLNF+2 1F MSB of NF/NR/NO Value for Display PLL(R/W) [OPLLNRO] OPLLNR OPLLNO OPLLNF <4:0> <6:5> <7> OPLLNR<4:0> value for display PLL OPLLNO<1:0> value for display PLL OPLLNF<8> Value for display PLL <7:0> OPLLNF<7:0> Value for display PLL Note: NR is OPLLNR+2, NO is OPLLNO+1 (c)2002,2003-Copyright by AverLogic Technologies, Corp. Version B1.0 39 AL260 Capture Control Group Registers (Accessible when BAS#0E = 01h) I. Capture Timing INDEX (HEX) 20 Register Description Register Name BITS Function Description Horizontal Capture Start LSB (R/W) [CAPHSTART] CapHStartL <7:0> Bits<7:0> of horizontal capture start position (Unit: 1 pixel) 21 Horizontal Capture Start MSB (R/W) [CAPHSTART] CapHStartH Reserved <3:0> <7:4> Bits<11:8> of horizontal capture start position Reserved 22 Horizontal Capture Source Size LSB (R/W) [CAPHSRCSIZE] CapHSrcSizeL <7:0> Bits<7:0> of horizontal capture source size (Unit: 1 pixel) 23 Horizontal Capture Source Size MSB (R/W) [CAPHSRCSIZE] CapHSrcSizeH Reserved <3:0> <7:4> Bits<11:8> of horizontal capture source size Reserved 24 Horizontal Capture Destination Size LSB (R/W) [CAPHDESTSIZE] CapHDestSizeL <7:0> Bits<7:0> of horizontal capture destination size (Unit: 1 pixel) 25 Horizontal Capture Destination Size MSB (R/W) [CAPHDESTSIZE] CapHDestSizeH Reserved <3:0> <7:4> Bits<11:8> of horizontal capture destination size Reserved 26 Vertical Capture Start LSB (R/W) [CAPVSTART] CapVStartL <7:0> Bits<7:0> of vertical capture start position (Unit: 1 line) 27 Vertical Capture Start MSB (R/W) [CAPVSTART] CapVStartH Reserved <2:0> <7:4> Bits<10:8> of vertical capture start position Reserved (c)2002,2003-Copyright by AverLogic Technologies, Corp. Version B1.0 40 AL260 28 Vertical Capture Source Size LSB (R/W) [CAPVSRCSIZE] CapVSrcSizeL 29 <7:0> Bits<7:0> of vertical capture source size (Unit: 1 line) Vertical Capture Source Size MSB (R/W) [CAPVSRCSIZE] CapVSrcSizeH Reserved <2:0> <7:4> Bits<10:8> of vertical capture source size Reserved 2A Vertical Capture Destination Size LSB (R/W) [CAPVDESTSIZE] CapVDestSizeL <7:0> Bits<7:0> of vertical capture destination size (Unit: 1 line). 2B Vertical Capture Destination Size MSB (R/W) [CAPVDESTSIZE] CapVDestSizeH Reserved <2:0> <7:4> Bits<10:8> of vertical capture destination size Reserved 2E Interlace Control (R/W) [INTERLACECTR] InterlaceEn FieldCap <0> <2:1> Enable interlace timing input Field capture into memory 00 01 10 11 Fieldoffset <7:4> Capture even and odd field into memory Capture odd field only Capture even field only Reserved Field capture offset 30 Horizontal Scale Down Ratio LSB (R/W) [HDNRATIO] HDnRatioL <7:0> Bits<7:0> of horizontal scale down ratio 31 Horizontal Scale Down Ratio MSB (R/W) [HDNRATIO] HDnRatioH Reserved <0> <7:1> Bit<8> of horizontal scale down ratio Reserved 32 Vertical Scale Down Ratio LSB (R/W) [VDNRATIO] VDnRatioL <7:0> Bits<7:0> of vertical scale down ratio 33 Vertical Scale Down Ratio MSB (R/W) [VDNRATIO] (c)2002,2003-Copyright by AverLogic Technologies, Corp. Version B1.0 41 AL260 VDnRatioH Reserved Note: <0> <7:1> Bit<8> of vertical scale down ratio Reserved HDNRATIO = CAPHDESTSIZE / CAPHSRCSIZE * 256 VDNRATIO = CAPVDESTSIZE / CAPVSRCSIZE * 256 II. VBI Input timing: VBI captured data is always been stored in DRAM address, starting at 0. To Disable VBI capture, set VBIVStart > VBIVEnd, and VBIHStart > VBIHEnd 34 VBI Vertical Start (R/W) [VBIVSTART] VBIVStart 35 <7:0> VBI vertical capture start position VBI Vertical End (R/W) [VBIVEND] VBIVend <7:0> VBI vertical capture end 36 VBI Horizontal Start (R/W) [VBIHSTART] VBIHStart <7:0> VBI horizontal capture start position 37 VBI Horizontal Size (R/W) [VBIVSIZE] VBIHSize <7:0> VBI horizontal capture size III. ITU-656 Detection: 38 ITU-656 Hsync Start (R/W) [656HSTART] 656HStart 39 <7:0> ITU656data horizontal sync start position, default value 20h ITU-656 Hsync End (R/W) [656HEND] 656HEnd <7:0> ITU656data horizontal sync end position, default value 80h 3A ITU-656 Vsync Start (R/W) [656VSTART] 656VStart <7:0> ITU656data vertical sync start position, default value 02h 3B ITU-656 Vsync End (R/W) [656VEND] (c)2002,2003-Copyright by AverLogic Technologies, Corp. Version B1.0 42 AL260 656VEnd IV: Position Detection: 50 Data Threshold for Position Detection (R/W) [POSDATATH] PosDataTh <7:0> Luma(brightness) threshold value <7:0> ITU656data vertical sync end position, default value 04h Note: CAP#50 is used to determine input non-blanking pixel for both horizontal and vertical direction. Any pixel luma value less than this value will be considered as blanking. 52 Horizontal Active Start LSB (R) [POSHDESTART] PosHDEStartL 53 <7:0> Bits<7:0> of detected horizontal active start position (Unit: 1 pixel) Horizontal Active Start MSB (R) [POSHDESTART] PosHDEStartH Reserved <2:0> <7:3> Bits<10:8> of detected horizontal active start position Reserved 54 Horizontal Active End LSB (R) [POSHDEEND] PosHDEEndL <7:0> Bits<7:0> of detected horizontal active start position (Unit: 1 pixel) 55 Horizontal Active End MSB (R) [POSHDEEND] PosHDEEndH Reserved <2:0> <7:3> Bits<10:8> of detected horizontal active end position Reserved 56 Vertical Active Start LSB (R) [POSVDESTART] PosVDEStartL <7:0> Bits<7:0> of detected vertical active start line (Unit: 1 line) 57 Vertical Active Start MSB (R) [POSVDESTART] PosVDEStartH Reserved <2:0> <7:3> Bits<10:8> of detected vertical active start line Reserved 58 Vertical Active End LSB (R) [POSVDEEND] PosVDEEndL <7:0> Bits <7:0> of detected vertical active end line (Unit: 1 line) (c)2002,2003-Copyright by AverLogic Technologies, Corp. Version B1.0 43 AL260 59 Vertical Active End MSB (R) [POSVDEEND] PosVDEEndH Reserved V: Mode Detection: <2:0> <7:3> Bits<10:8> of detected vertical active end line Reserved 62 Horizontal Capture Total Counter LSB (R) [CAPHTOTALCNT] CapHtotalCntL <7:0> Bits<7:0> of horizontal total count value 63 Horizontal Capture Total Counter MSB (R) [CAPHTOTALCNT] CapHtotalCntH Reserved <2:0> <7:3> Bits<10:8> of horizontal total count value Reserved 64 Vertical Capture Total Counter LSB (R) [CAPVTOTALCNT] CapVtotalCntL <7:0> Bits<7:0> of vertical total count value 65 Vertical Capture Total Counter MSB (R) [CAPVTOTALCNT] CapVtotalCntH Reserved <2:0> <7:3> Bits<10:8> of vertical total count value Reserved 73 Tune Input Clock Phase (R/W) [TUNEINCLK] TuneInclk <2:0> <4:3> Phase delay number(8 steps) Phase delay types 00 01 10 11 Reserved <7:5> Inclk Inclk + delay phase Inversed Inclk Inversed Inclk + delay phase Reserved (c)2002,2003-Copyright by AverLogic Technologies, Corp. Version B1.0 44 AL260 Memory Control Group Registers (Accessible when BAS#0E = 02h) I.DRAM control INDEX (HEX) 20 Register Description Register Name BITS Function Description DRAM Access control (R/W) [DRAMACCESSCTRL] InputEnable Reserved PowerUp OutputEnable Reserved RefreshEnable PowerDown SetMode <0> <1> <2> <3> <4> <5> <6> <7> Enable input data to DRAM Reserved Enable power up Enable output data from DRAM Reserved Enable DRAM refresh Enable power down Enable DRAM setmode cycle 21 DRAM Write (R/W) [DRAMWRITE] PMCLKSel <0> Select DRAM read clock signal path 0 1 WriteMask1 WriteMask2 SoftRest DataDelay DataRdyDelay <1> <2> <3> <5:4> <7:6> Internal loop External loop from pad MCLK to PMCLK Write mask of DRAM byte 0, 1 Write mask of DRAM byte 2 Software Reset DRAM data delay DRAM data ready delay 22 Output & FIFO Control (R/W) [OUTFIFOCTRL] OutputLevel Reserved <3:0> <7:4> Output FIFO level control Reserved 23 Input FIFO Control (R/W) [INFIFOCTRL] InputLevel Reserved <3:0> <7:4> Input FIFO level control Reserved (c)2002,2003-Copyright by AverLogic Technologies, Corp. Version B1.0 45 AL260 Note: These are DRAM FIFO water mark, when FIFO reach this urgent level, the corresponding video source needs to be serviced(R/W or to/from DRAM) 24~27: Reserved 28 DRAM Minimum Refresh (R/W) [DRAMMINREFRESH] MinRefresh <7:0> Minimum refresh requirement within the period of a output VSYNC, usually 1/60 sec 29 DRAM Control 0 (R/W) [DRAMCTRL] TRAS <1:0> DRAM RAS control signal 00 01 01 11 TRC <4:2> 000 001 001 011 100 101 101 111 TRCD <5> 0 1 TRP <6> 0 1 TRPD <7> 0 1 5 memory clocks 6 memory clocks 7 memory clocks 8 memory clocks 7 memory clocks 8 memory clocks 9 memory clocks 10 memory clocks 11 memory clocks 12 memory clocks 13 memory clocks 14 memory clocks No delay Delay 1 memory clock No delay Delay 1 memory clock No delay Delay 1 memory clock DRAM RC control signal DRAM RCD control signals DRAM RP control signal DRAM RPD control signal (c)2002,2003-Copyright by AverLogic Technologies, Corp. Version B1.0 46 AL260 2A DRAM Control 1 (R/W) [DRAMCTRL] TWR <0> DRAM WR control signal 0 1 TCL <1> 0 1 TRW <2> 0 1 MemConfig <4:3> 00 01 10 11 BankConfig <5> 0 1 Reserved TXSR <6> <7> Tie to 1 DRAM XSR control signal No delay Delay 1 memory clock No delay Delay 1 memory clock No delay Delay 1 memory clock 16Mb 64Mb Reserved Reserved A22, 0-4M = bank 0, 4-8M = bank 1 A21, 4-6M = bank 0, 6-8M = bank 1 DRAM CL control signal DRAM RW control signal SDRAM Size Bank selector Note: MEM#29&2A is SDRAM timing parameters. Default value: MEM#29="ef", MEM#2A="4f" 2B DRAM Read Address 0 (R/W) [DRAMRADDR] MemReadAddr0 2C <7:0> Bits<7:0> of DRAM read address. (unit: 2 pixels) DRAM Read Address 1 (R/W) [DRAMRADDR] MemReadAddr1 <7:0> Bits<15:8> of DRAM read address 2D DRAM Read Address 2 (R/W) [DRAMRADDR] MemReadAddr2 Reserved <4:0> <7:5> Bits<20:16> of DRAM read address Reserved 30 XY Mirror Input (R/W) [XYMIRRORIN] (c)2002,2003-Copyright by AverLogic Technologies, Corp. Version B1.0 47 AL260 InputFlipX InputFlipY Reserved 31 <0> <1> <7:2> Enable X mirror capture (horizontally captured in the reversed direction) Enable Y mirror capture (vertically captured in the reversed direction, i.e. up side down capture) Reserved XY Mirror Output (R/W) [XYMIRROROUT] OutputFlipX OutputFlipY Reserved <0> <1> <7:2> Enable X mirror display (horizontally display in the reversed direction) Enable Y mirror display (vertically displayed in the reversed direction, i.e. up side down display) Reserved 32 Skip Mode (R/W) [SKIPMODE] InputSkip <1:0> DRAM input address pointer incremental unit 00 01 10 2 fields/1 frame stockpile, even1, odd1, even1, odd1 ...., Note: Stride >= size Reserved 4 fields/2frames stockpile F1(1),F2(1),F3(1),F4(1),F1(2),F2(2),F3(2)... Note: Stride >= size * 4 11 Reserved TwoField Reserved MemControlEn DbufferEn Reserved <2> <3> <4> <5> <6> <7> Reserved Reserved Two field mode enable Reserved 0 1 Disable sdram controller Enable sdram controller Dobule buffering enable Reserved II. DRAM input window control 33 DRAM Input Start (R/W) [DRAMINSTART] DRAMINStart <7:0> Input DRAM address start (Unit: 8192 pixels) (c)2002,2003-Copyright by AverLogic Technologies, Corp. Version B1.0 48 AL260 34 DRAM Input Horizontal Stride (R/W) [DRAMINHSTRIDE] DRAMINHStride <7:0> Input DRAM horizontal stride (Unit: 4 pixels) 35 DRAM Input Horizontal Size (R/W) [DRAMINHSIZE] DRAMINHSize <7:0> Input DRAM horizontal size (Unit: 4 pixels) Note: Set stride value at 64/128/256 boundary, will better ease DRAM timing. DRAMINHSIZE = CAPHDESTSIZE(CAP#25&24) / 4 III. DRAM window copy control 39 Window Copy Source Start LSB (R/W) [WCSRCSTART] GSInputStart1 3A <7:0> Bits<7:0> of GS input DRAM address start. (Unit: 8192 pixels) Window Copy Source Start (R/W) [WCSRCSTART] GSInputStart2 <7:0> Bits<15:8> of GS input DRAM address start 3B Window Copy Source Start MSB (R/W) [WCSRCSTART] GSInputStart3 Reserved <3:0> <7:4> Bits<18:16> of GS input DRAM address start Reserved 3C Window Copy Source Stride (R/W) [GSDRAMINPUTSTRIDE] GSIStride <7:0> GS input DRAM stride. (8 pixels) 3D Window Copy Size (R/W) [GSDRAMINPUTSIZE] GSHSize <7:0> GS input DRAM size. (Unit: 8 pixels) 3E Direct Write Stride (R/W) [WCSTRIDE] WCStride <7:0> DRAM window copy stride. (Unit: 8 pixels) 3F Window Copy Destination Start LSB (R/W) [WCDESTSTART] WCSrcStart1 <7:0> Bits<7:0> of DRAM window copy source address start. (Unit: 8 pixels) (c)2002,2003-Copyright by AverLogic Technologies, Corp. Version B1.0 49 AL260 40 Window Copy Destination Start (R/W) [WCDESTSTART] WCDestStart2 <7:0> Bits<15:8> of DRAM window copy source address start 41 Window Copy Destination Start MSB (R/W) [WCDESTSTART] WCDestStart3 Reserved <3:0> <7:4> Bits<20:16> of DRAM window copy source address start Reserved Note: After writing to MEM#41, the Window Copy operation will be carried out. 42 Direct Read/Write Address LSB (R/W) [DASTART] DAddrStart1 <7:0> Bits<7:0> of DRAM window copy source address start. (Unit: 8 pixels) 43 Direct Read/Write Address (R/W) [DASTART] DAddrStart2 44 <7:0> Bits<15:8> of DRAM window copy source address start Direct Read/Write Address MSB (R/W) [DASTART] DAddrStart3 Reserved <3:0> <7:4> Bits<20:16> of DRAM window copy source address start Reserved 45 Window Copy Size (R/W) [WCSIZE] WCSize <7:0> DRAM Directly Write size. (Unit: 8 pixels) or DRAM window copy total lines [7:0] for Window Copy. 46 Window Copy Line Total (R/W) [WCLINETOTAL] WCLineTotal <7:0> DRAM window copy total lines[2:0]. (1 line) IV. DRAM output window control 47 DRAM Output Start (R/W) [DRAMOUTSTART] DRAMOutStart 48 <7:0> Output DRAM address start. (Unit: 8192 pixels) DRAM Output Horizontal Stride (R/W) [DRAMOUTHSTRIDE] (c)2002,2003-Copyright by AverLogic Technologies, Corp. Version B1.0 50 AL260 DRAMOutHStride 49 <7:0> Output DRAM horizontal stride. (Unit: 4/8/12 pixels) DRAM Output Horizontal Size (R/W) [DRAMOUTHSIZE] DRAMOutHSize <7:0> Output DRAM horizontal size. (Unit: 4/8/12 pixels) DRAMOHSIZE = DISHSRCSIZE(DIS#41&40) / 4 4D VBI Start Address LSB (R/W) [VBISTART] VBIAddrStart1 4E <7:0> Bit<7:0> of VBI starting address. VBI Start Address (R/W) [VBISTART] VBIAddrStart2 <7:0> Bit<15:8> of VBI starting address. 4F VBI Start Address MSB (R/W) [VBISTART] VBIAddrStart3 Reserved <3:0> <7:4> Bit<19:16> of VBI starting address. Reserved 50 Front Motion Detect Control (R/W) [FRONTM] FrontMYth EnFrontM <6:0> <7> Y threshold Value for Front Motion Enable Front Motion Detection 51 Tune Memory Write Clock Phase (R/W) [TUNEMCLK] TuneMclk <2:0> <4:3> Phase delay number(8 steps) Phase delay types 00 01 10 11 Reserved <7:5> Mclk Mclk + delay phase Inversed Mclk Inversed Mclk + delay phase Reserved 52 Tune Memory Read Clock Phase (R/W) [TUNEPMCLK] TunePMclk <2:0> <4:3> Phase delay number(8 steps) Phase delay types 00 PMclk (c)2002,2003-Copyright by AverLogic Technologies, Corp. Version B1.0 51 AL260 01 10 11 Reserved V. DRAM data port <7:5> PMclk + delay phase Inversed PMclk Inversed PMclk + delay phase Reserved 60 Read Status (R) [READSTATUS] Status Reserved <0> <7:1> Data Ready Reserved 61 Byte 0 (R)(W) [BYTE0] RByte0(R) WByte0(W) <7:0> <7:0> Bits<7:0> of DRAM for read-out Bits<7:0> of Pixel 0 for 16-bit mode Write, or Dummy field for 24-bit mode Write 62 Byte 1 (R)(W) [BYTE1] RByte1(R) WByte1(W) <7:0> <7:0> Bits<15:8> of DRAM read-out Bits<15:8> of Pixel 0 for 16-bit mode Write, or Blue field for 24-bit mode Write 63 Byte 2 (R)(W) [BYTE2] RByte2(R) WByte2(W) <7:0> <7:0> Bits<23:16> of DRAM read-out Bits<7:0> of Pixel 1 for 16-bit mode Write, or Green field for 24-bit mode Write 64 Byte 3 (R)(W) [BYTE3] RByte3(R) WByte3(W) <7:0> <7:0> Bits<31:24> of DRAM read-out <15:8> of Pixel 1 for 16-bit mode Write, or Red field for 24-bit mode Write 65 Byte 4 (R) [BYTE4] RByte4 <7:0> Bits<39:32> of DRAM read-out (c)2002,2003-Copyright by AverLogic Technologies, Corp. Version B1.0 52 AL260 66 Byte5 (R) [BYTE5] RByte4 <7:0> Bits<47:40> of DRAM read-out DRAM data read ports are defined in MEM#61~66. MemReadAddr is defined in MEM#42~44. After reading MEM#60, the read cycle will be strobe if bit-0 is 0. MEM#60 should be read until bit 0 is 1. Then, read MEM#61~66 for the data read from SDRAM. (c)2002,2003-Copyright by AverLogic Technologies, Corp. Version B1.0 53 AL260 Display Control Group Registers (Accessible when BAS#0E = 03h) I. Display Timing INDEX (HEX) 20 Register Description Register Name BITS Function Description Horizontal Display Total LSB (R/W) [DISHTOTAL] DisHTotalL <7:0> Bits<7:0> of display horizontal total (Unit: 1 pixel) 21 Horizontal Display Total MSB (R/W) [DISHTOTAL] DisHTotalH Reserved <3:0> <7:4> Bits<11:8> of display horizontal total Reserved 22 Horizontal Display Sync LSB (R/W) [DISHSEND] DisHSEndL <7:0> Bits<7:0> of display horizontal sync end (Unit: 1 pixel) 23 Horizontal Display Sync MSB (R/W) [DISHSEND] DisHSEndH Reserved <3:0> <7:4> Bits<11:8> of display horizontal sync end Reserved Note: Horizontal sync start at position 1. 24 Horizontal Display Start LSB (R/W) [DISHDESTART] DisHDEStartL 25 <7:0> Bits<7:0> of horizontal display start (Unit: 1 pixel) Horizontal Display Start MSB (R/W) [DISHDESTART] DisHDEStartH Reserved <3:0> <7:4> Bits<11:8> of horizontal display start Reserved 26 Horizontal Display End LSB (R/W) [DISHDEEND] DisHDEEndL <7:0> Bits<7:0> of horizontal display end (Unit: 1 pixel) 27 Horizontal Display End MSB (R/W) [DISHDEEND] DisHDEEndH <3:0> Bits<11:8> of horizontal display end (c)2002,2003-Copyright by AverLogic Technologies, Corp. Version B1.0 54 AL260 Reserved 28 <7:4> Reserved Display Vertical Total LSB (R/W) [DISVTOTAL] DisVTotalL <7:0> Bits<7:0> of display vertical total (Unit: 1 pixel) 29 Display Vertical Total MSB (R/W) [DISVTOTAL] DisVTotalH Reserved <3:0> <7:4> Bits <11:8> of display vertical total Reserved 2A Display Vertical Sync LSB (R/W) [DISVSEND] DisVSEndL <7:0> Bits<7:0> of display vertical sync end (Unit: 1 pixel) 2B Display Vertical Sync MSB (R/W) [DISVSEND] DisVSEndH Reserved <3:0> <7:4> Bits<11:8> of display vertical sync end Reserved Note: Vertical sync start at line 1. 2C Vertical Display Start LSB (R/W) [DISVDESTART] DisVDEStartL 2D <7:0> Bits<7:0> of vertical display start (Unit: 1 pixel) Vertical Display Start MSB (R/W) [DISVDESTART] DisVDEStartH Reserved <3:0> <7:4> Bits<11:8> of vertical display start Reserved 2E Vertical Display End LSB (R/W) [DISVDEEND] DisVDEEndL <7:0> Bits<7:0> of vertical display end(Unit: 1 pixel) 2F Vertical Display End MSB (R/W) [DISVDEEND] DisVDEEndH Reserved <3:0> <7:4> Bits<11:8> of vertical display end Reserved II. Window Output Timing (c)2002,2003-Copyright by AverLogic Technologies, Corp. Version B1.0 55 AL260 30 Horizontal Display Active Start LSB (R/W) [DISHDESTART] DisHDEStartL 31 <7:0> Bits<7:0> of horizontal display active start (Unit: 1 pixel) Horizontal Display Active Start MSB (R/W) [DISHDESTART] DisHDEStartH Reserved <3:0> <7:4> Bits<11:8> of horizontal display active start Reserved 32 Horizontal Display Active End LSB (R/W) [DISHDEEND] DisHDEEndL <7:0> Bits<7:0> of horizontal display active end (Unit: 1 pixel) 33 Horizontal Display Active End MSB (R/W) [DISHDEEND] DisHDEEndH Reserved <3:0> <7:4> Bits<11:8> of horizontal display active end Reserved 34 Vertical Display Active Start LSB (R/W) [DISVDESTART] DisVDEStartL <7:0> Bits<7:0> of vertical display active start (Unit: 1 pixel) 35 Vertical Display Active Start MSB (R/W) [DISVDESTART] DisVDEStartH Reserved <3:0> <7:4> Bits<11:8> of vertical display active start Reserved 36 Vertical Display Active End LSB (R/W) [DISVDEEND] DisVDEEndL <7:0> Bits<7:0> of vertical display active end (Unit: 1 pixel) 37 Vertical Display Active End MSB (R/W) [DISVDEEND] DisVDEEndH Reserved <3:0> <7:4> Bits<11:8> of vertical display active end Reserved III. Zoom In Control Registers 40 Horizontal Display Source Size LSB (R/W) [DISHSRCSIZE] DisHSrcSizeL 41 <7:0> Bits<7:0> of horizontal display source size (Unit: 1 pixel) Horizontal Display Source Size MSB (R/W) [DISHSRCSIZE] (c)2002,2003-Copyright by AverLogic Technologies, Corp. Version B1.0 56 AL260 DisHSrcSizeH Reserved 42 <3:0> <7:4> Bits<11:8> of horizontal display source size Reserved Horizontal Display Destination Size LSB (R/W) [DISHDESTSIZE] DisHDestSizeL <7:0> Bits<7:0> of horizontal display destination size (Unit: 1 pixel). 43 Horizontal Display Destination Size MSB (R/W) [DISHDESTSIZE] DisHDestSizeH Reserved <3:0> <7:4> Bits<11:8> of horizontal display destination size Reserved 44 Vertical Display Source Size LSB (R/W) [DISVSRCSIZE] DisVSrcSizeL <7:0> Bits<7:0> of vertical display source size (Unit:1 pixel) 45 Vertical Display Source Size MSB (R/W) [DISVSRCSIZE] DisVSrcSizeH Reserved <3:0> <7:4> Bits<11:8> of vertical display source size Reserved 46 Vertical Display Destination Size LSB (R/W) [DISVDESTSIZE] DisVDestSizeL <7:0> Bits<7:0> of vertical display source size (Unit:1 pixel) 47 Vertical Display Destination Size MSB (R/W) [DISVDESTSIZE] DisVDestSizeH Reserved <3:0> <7:4> Bits<11:8> of vertical display destination size Reserved DISVDESTSIZE >= DISVSRCSIZE Note : DISHDESTSIZE >= DISHSRCSIZE, 48 Zoom In Filter Control (R/W) [ZOOMFCTRL] VZoomEn HZoomEn Reserved <0> <1> <7:2> Enable vertical scale-up filtering Enable horizontal scale-up filtering Reserved 4A Horizontal Scale Up Ratio LSB (R/W) [HUPRATIO] HUpRatioL <7:0> Bits<7:0> of horizontal scale up ratio (c)2002,2003-Copyright by AverLogic Technologies, Corp. Version B1.0 57 AL260 4B Horizontal Scale Up Ratio MSB (R/W) [HUPRATIO] HUpRatioH 4A <7:0> Bits<15:8> of horizontal scale up ratio Delta Horizontal Scale Up Ratio LSB (R/W) [DELTAHUPRATIO] DeltaHUpRatioL <7:0> Bits<7:0> delta of horizontal scale up ratio for Keystone 4B Delta Horizontal Scale Up Ratio MSB (R/W) [DELTAHUPRATIO] DeltaHUpRatioH HDEStartInc <3:0> <5:4> Bits<11:8> delta of horizontal scale up ratio for Keystone Delta of starting point of horizontal DE for Keystone 00 01 10 11 HDEEndInc <7:6> 00 01 10 11 Added by 0 Added by 1 Added by 0 Substrate by 1 Added by 0 Added by 1 Added by 0 Substrate by 1 Delta of Ending point of horizontal DE for Keystone Note: This definition is valid when DIS#CB<4>='1' and used in Keystone 4C Vertical Scale Up Ratio LSB (R/W) [VUPRATIO] VUpRatioL 4D <7:0> Bits<7:0> of vertical scale up ratio Vertical Scale Up Ratio MSB (R/W) [VUPRATIO] VUpRatioH <7:0> Bits<15:8> of vertical scale up ratio Note: HUPRATIO = DISHSRCSIZE / DISHDESTSIZE * 8192 Note: VUPRATIO = DISVSRCSIZE / DISVDESTSIZE * 8192 4E Horizontal Scale Up Initial Phase LSB (R/W) [HPHASE] HUpPhaseL 4F <7:0> Bit<7:0> of horizontal scale up initial phase Horizontal Scale Up Initial Phase MSB (R/W) [HPHASE] HUpPhaseH <7:0> Bit<15:8> of horizontal scale up initial phase (c)2002,2003-Copyright by AverLogic Technologies, Corp. Version B1.0 58 AL260 50 Vertical Scale Up Initial Phase LSB (R/W) [VPHASE] VUpPhaseL <7:0> Bit<7:0> of vertical scale up initial phase 51 Vertical Scale Up Initial Phase MSB (R/W) [VPHASE] VUpPhaseH <7:0> Bit<15:8> of vertical scale up initial phase 54 Output Mode (R/W) [OUTPUTMODE] OutputMode <1:0> Output enable 00 01 10 11 Reserved DitherMode <4:2> <5> Enable Reserved Reserved Disable, Zero output Reserved Enable dither output 0 1 No dither 8 bits to 6 bits Reserved LutEn 55 <6> <7> Reserved Enable built-in LUT look-up table LUT Write Index (R/W) [LUTWINDEX] LUTWIndex <7:0> LUT access index 5C LUT Red Color LSB (R/W) [LUTRED] LUTRed <7:0> LUT red color port 5D LUT Green Color LSB (R/W) [LUTGREEN] LUTGreen <7:0> LUT green color port 5E LUT Blue Color LSB (R/W) [LUTBLUE] LUTBlue <7:0> LUT blue color port 5F LUT Read/Write Trigger (R/W) [LUTWEN] Reserved <5:0> Reserved (c)2002,2003-Copyright by AverLogic Technologies, Corp. Version B1.0 59 AL260 LUTWEn <7:6> Write color field enable 00 01 10 11 56 Red, Green and Blue written into LUT Only Red is written into LUT Only Green written into LUT Only Blue written into LUT Pattern Generator and GPO (R/W) [PATTERNGEN] PatternMode <1:0> 00 01 10 11 PatternEn GPO <4> <7:5> Fram line Color bar Gray level Line moier Enable pattern generation General purpose output port Note: Set register GPO(DIS#56<7:5>) value will effect pin GPO2~0 output status in phase IV. OSD Color Registers 58 OSD Write Address LSB (R/W) [OSDRAMWADDR] OSDRamWAddrL 59 <7:0> Bit<7:0> of OSD ram write address OSD Write Address MSB (R/W) [OSDRAMWADDR] OSDRamWAddrH Reserved <2:0> <7:3> Bit<10:8> of OSD ram write address Reserved 5A OSD Write Data Port (W) [OSDRAMWDATA] OSDWData <7:0> OSD ram write data port 60 Color 0 Red (R/W) [COLOR0RED] Color0Red <7:0> Color 0 Red Component 61 Color 0 Green (R/W) [COLOR0GREEN] Color0Green <7:0> Color 0 Green Component (c)2002,2003-Copyright by AverLogic Technologies, Corp. Version B1.0 60 AL260 62 Color 0 Blue (R/W) [COLOR0RED] Color0Blue 63 <7:0> Color 0 Blue Component Color 1 Red (R/W) [COLOR1RED] Color1Red <7:0> Color 1 Red Component 64 Color 1 Green (R/W) [COLOR1GREEN] Color1Green <7:0> Color 1 Green Component 65 Color 1 Blue (R/W) [COLOR1BLUE] Color1Blue <7:0> Color 1 Blue Component 66 Color 2 Red (R/W) [COLOR2RED] Color2Red <7:0> Color 2 Red Component 67 Color 2 Green (R/W) [COLOR2GREEN] Color2Green <7:0> Color 2 Green Component 68 Color 2 Blue (R/W) [COLOR2BLUE] Color2Blue <7:0> Color 2 Blue Component 69 Color 3 Red (R/W) [COLOR3RED] Color3Red <7:0> Color 3 Red Component 6A Color 3 Green (R/W) [COLOR3GREEN] Color3Green <7:0> Color 3 Green Component 6B Color 3 Blue (R/W) [COLOR3BLUE] Color3Blue <7:0> Color 3 Blue Component 6C Color 4 Red (R/W) [COLOR4RED] Color4Red <7:0> Color 4 Red Component 6D Color 4 Green (R/W) [COLOR0GREEN] (c)2002,2003-Copyright by AverLogic Technologies, Corp. Version B1.0 61 AL260 Color4Green 6E <7:0> Color 4 Green Component Color 4 Blue (R/W) [COLOR4BLUE] Color4Blue <7:0> Color 4 Blue Component 6F Color 5 Red (R/W) [COLOR5RED] Color5Red <7:0> Color 5 Red Component 70 Color 5 Green (R/W) [COLOR5GREEN] Color5Green <7:0> Color 5 Green Component 71 Color 5 Blue (R/W) [COLOR5BLUE] Color5Blue <7:0> Color 5 Blue Component 72 Color 6 Red (R/W) [COLOR6RED] Color6Red <7:0> Color 6 Red Component 73 Color 6 Green (R/W) [COLOR6GREEN] Color6Green <7:0> Color 6 Green Component 74 Color 6 Blue (R/W) [COLOR6BLUE] Color6Blue <7:0> Color 6 Blue Component 75 Color 7Red (R/W) [COLOR7RED] Color7Red <7:0> Color 7 Red Component 76 Color 7 Green (R/W) [COLOR7GREEN] Color7Green <7:0> Color 7 Green Component 77 Color 7 Blue (R/W) [COLOR7BLUE] Color7Blue <7:0> Color 7 Blue Component V. OSD Control Register (c)2002,2003-Copyright by AverLogic Technologies, Corp. Version B1.0 62 AL260 78 OSD Color Select (R/W) [OSDCOLORSEL] Osd1ColorSel <1:0> OSD1 color selection, 8 colors only apply when Font2byte= '1' and PixDepth1= '1' 00 01 10 11 Osd2ColorSel <3:2> select OSD1 colors from index 3..0 select OSD1 colors from index 7..4 select OSD1 colors from index 7..0 Reserved OSD2 color selection, 8 colors only apply when Font2byte= '1' and PixDepth2= '1' 00 01 10 11 select OSD2 colors from index 3..0 select OSD2 colors from index 7..4 select OSD2 colors from index 7..0 Reserved Font2byte Reserved 79 <4> <7:5> Two-byte font charter code mode, effective only when RomMode = '1' Reserved Blink Time (R/W) [BLINKTIME] BlinkTimer BlinkType <6:0> <7> Blinking timing value 0 1 Reverse color Bypass Note: OSD Blinking frequency = Vsync frequency / BlinkTimer 80 OSD Modes (R/W) [OSDMODE] RomMode <0> Enable ROM mode 0 1 Reserved Number <1> <7:2> Tie to 0 Adjust rom address width to access external rom data Internal RAM mode External ROM mode Note: The method of select the Number value show on OSD application note 81 Logic Operation (R/W) [FOREOP] (c)2002,2003-Copyright by AverLogic Technologies, Corp. Version B1.0 63 AL260 Color0Op <1:0> Logic operation between color 0 and video 00 01 10 11 Color1Op <3:2> 00 01 10 11 Color2Op <5:4> 00 01 10 11 Color3Op <7:6> 00 01 10 11 83 Logic Operation (R/W) [FOREOP] Color4Op <1:0> Logic operation between color 4 and video 00 01 10 11 Color5Op <3:2> 00 01 10 11 Color6Op <5:4> 00 NOP, show only OSD OR, video or color 4 AND, video and color 4 XOR, video xor color 4 NOP, show only OSD OR, video or color 5 AND, video and color 5 XOR, video xor color 5 NOP, show only OSD NOP, show only OSD OR, video or color 0 AND, video and color 0 XOR, video xor color 0 NOP, show only OSD OR, video or color 1 AND, video and color 1 XOR, video xor color 1 NOP, show only OSD OR, video or color 2 AND, video and color 2 XOR, video xor color 2 NOP, show only OSD OR, video or color 3 AND, video and color 3 XOR, video xor color 3 Logic operation between color 1 and video Logic operation between color 2 and video Logic operation between color 3 and video Logic operation between color 5 and video Logic operation between color 6 and video (c)2002,2003-Copyright by AverLogic Technologies, Corp. Version B1.0 64 AL260 01 10 11 Color7Op <7:6> 00 01 10 11 Note: Color 0 ~ 7 are defined in DIS#60~77. 82 Fading Alpha Value (R/W) [FADEALPHA] FadeAlpha Reserved <5:0> <7:6> The alpha factor for fading effect ranging Reserved OR, video or color 6 AND, video and color 6 XOR, video xor color 6 NOP, show only OSD OR, video or color 7 AND, video and color 7 XOR, video xor color 7 Logic operation between color 7 and video Note: FADEALPHA range from 00h to 20h, there is 33-level of fade-in/fade-out effect. Output = Image * FADEALPHA/32 + OSD * (1 - (FADEALPHA /32)) Show only OSD: FADEALPHA = "000000" --- minimum alpha value(00h) Show only Image: FADEALPHA = "100000" --- maximum alpha value(20h) VI. OSD 1 Registers 84 OSD1 Control (R/W) [OSDCONTROL1] PixDepth1 <0> Number of bits per pixel of OSD1 0 1 BlinkEn1 <1> 0 1 HZoom1 <3:2> 00 01 10 11 One bit per pixel Two bits per pixel Disable blinking Enable blinking OSD1 pixel H size equals to 1X of video pixel OSD1 pixel H size equals to 2X of video pixel OSD1 pixel H size equals to 4X of video pixel OSD1 pixel H size equals to 8X of video pixel OSD1 blinking enable, effective when RomMode = `1' OSD1 horizontal zoom factor (c)2002,2003-Copyright by AverLogic Technologies, Corp. Version B1.0 65 AL260 VZoom1 <5:4> OSD1 vertical zoom factor 00 01 10 11 Reserved OsdEn1 <6> <7> OSD1 pixel V size equals to 1X of video pixel OSD1 pixel V size equals to 2X of video pixel OSD1 pixel V size equals to 4X of video pixel OSD1 pixel V size equals to 8X of video pixel Reserved OSD1 enable 0 1 Disable OSD1 Enable OSD1 85 OSD1 ROM Start Address (R/W) [ROMSTARTADDR1] RomStAddr1H <7:0> Bits<11:4> of OSD1 ROM start address (Unit: 16 bytes) 86 OSD1 Font Address Unit (R/W) [FONTADDRUNIT1] RomStAddr1L FontAddrUnit1 <3:0> <7:4> Bits<3:0> OSD1 ROM start address (Unit: 16 bytes) OSD1 font address unit (n), font address is multiple of 2(n+5) bytes, max. is 216 90 OSD1 Horizontal Start (R/W) [OSDHSTART1] OsdHStart1 <7:0> On Screen Display horizontal start position (Unit: 8 video pixels) 91 OSD1 Vertical Start (R/W) [OSDVSTART1] OsdVStart1 <7:0> On Screen Display vertical start position (Unit: 4 video lines) 92 OSD1 RAM Start Address (R/W) [RAMADDRST1] RamAddrSt1 <7:0> OSD1 RAM start address (Unit: 8 bytes) 8B OSD1 RAM Horizontal Stride MSB (R/W) [RAMSTRIDE1] RamStride1H Reserved <1:0> <7:2> Bits <9:8> of OSD1 RAM line stride (Unit: 1 bytes) Reserved 93 OSD1 RAM Horizontal Stride LSB (R/W) [RAMSTRIDE1] RamStride1L <7:0> Bits<7:0> of OSD1 RAM line stride(Unit: 1 bytes) (c)2002,2003-Copyright by AverLogic Technologies, Corp. Version B1.0 66 AL260 94 OSD1 Bitmap Horizontal Size LSB (R/W) [BMAPHSIZE1] BmapHSize1L 95 <7:0> Bits<7:0> of OSD1 horizontal bitmap size (Unit: 1 OSD pixel) OSD1 Bitmap Horizontal Size MSB (R/W) [BMAPHSIZE1] BmapHSize1H Reserved <1:0> <7:2> Bits<9:8> of OSD1 bitmap horizontal size Reserved 96 OSD1 Bitmap Horizontal Total Pixels LSB (R/W) [BMAPHTOTAL1] BmapHTotal1L <7:0> Bits<7:0> of OSD1 bitmap horizontal total (Unit: 1 OSD pixel) 97 OSD1 Bitmap Horizontal Total Pixels MSB (R/W) [BMAPHTOTAL1] BmapHTotal1H Reserved <1:0> <7:2> Bits<9:8> of OSD1 bitmap horizontal total Reserved 98 OSD1 Bitmap Vertical Size LSB (R/W) [BMAPVSIZE1] BmapVSize1L <7:0> Bits<7:0> of OSD1 bitmap vertical size (Unit: 1 OSD line) 99 OSD1 Bitmap Vertical Size MSB (R/W) [BMAPVSIZE1] BmapVSize1H Reserved <1:0> <7:2> Bits<9:8> of OSD1 bitmap vertical size Reserved 9A OSD1 Bitmap Vertical total Lines LSB (R/W) [BMAPVTOTAL1] BmapVTotal1L <7:0> Bits<7:0> of OSD1 bitmap vertical total(Unit: 1 OSD line) 9B OSD1 Bitmap Vertical Total Lines MSB (R/W) [BMAPVTOTAL1] BmapVTotal1H Reserved <1:0> <7:2> Bits<9:8> of OSD1 bitmap vertical total Reserved 9C OSD1 Icon Horizontal Total (R/W) [ICONHTOTAL1] IconHtotal1 <7:0> OSD1 horizontal icon total (Unit: 1 icon) 9D OSD1 Icon Vertical Total (R/W) [ICONVTOTAL1] IconVTotal1 <7:0> OSD1 vertical icon total (Unit: 1 icon) (c)2002,2003-Copyright by AverLogic Technologies, Corp. Version B1.0 67 AL260 AE OSD1 Font Line Size (R/W) [FONTLINESIZE1] Fontlinesize1 VII. OSD 2 Registers <7:0> memory size of a line of font (Unit: 1 byte) 88 OSD2 Control (R/W) [OSDCONTROL2] PixDepth2 <0> Number of bits per pixel of OSD2 0 1 BlinkEn2 <1> 0 1 Hzoom2 <3:2> 00 01 10 11 Vzoom2 <5:4> 00 01 10 11 Reserved OsdEn2 <6> <7> One bit per pixel Two bits per pixel Disable blinking Enable blinking OSD pixel H size equals to 1X of video pixel OSD pixel H size equals to 2X of video pixel OSD pixel H size equals to 4X of video pixel OSD pixel H size equals to 8X of video pixel OSD pixel V size equals to 1X of video pixel OSD pixel V size equals to 2X of video pixel OSD pixel V size equals to 4X of video pixel OSD pixel V size equals to 8X of video pixel OSD2 blinking enable, effective when RomMode = `1' OSD2 horizontal zoom factor OSD2 vertical zoom factor Reserved OSD2 enable 0 1 Disable OSD2 Enable OSD2 89 OSD2 ROM Start Address (R/W) [ROMSTARTADDR2] RomStAddr1H <7:0> Bits<11:4> of OSD2 ROM start address (Unit: 16 bytes) 8A OSD2 Font Address Unit (R/W) [FONTADDRUNIT2] RomStAddr2L FontAddrUnit2 <3:0> <7:4> Bits<3:0> OSD2 ROM start address (Unit: 16 bytes) OSD1 font address unit (n), font address is multiple of 2(n+5) bytes, max. is 216 (c)2002,2003-Copyright by AverLogic Technologies, Corp. Version B1.0 68 AL260 A0 OSD2 Horizontal Start (R/W) [OSDHSTART2] OsdHStart2 <7:0> On Screen Display horizontal start position (Unit: 8 video pixels) A1 OSD2 Vertical Start (R/W) [OSDVSTART1] OsdVStart2 <7:0> On Screen Display vertical start position (Unit: 4 video lines) A2 OSD2 RAM Start Address (R/W) [RAMADDRST2] RamAddrSt2 <7:0> OSD2 RAM start address (Unit: 8 bytes) 8C OSD2 RAM Horizontal Stride MSB (R/W) [RAMSTRIDE2] RamStride2H Reserved <1:0> <7:2> Bits <9:8> of OSD2 RAM line stride (Unit: 1 bytes) Reserved A3 OSD2 RAM Horizontal Stride LSB (R/W) [RAMSTRIDE2] RamStride2L <7:0> Bits<7:0> of OSD2 RAM line stride (Unit: 1 bytes) A4 OSD2 Bitmap Horizontal Size LSB (R/W) [BMAPHSIZE2] BmapHSize2L <7:0> Bits<7:0> of OSD1 horizontal bitmap size (Unit: 1 OSD pixel) A5 OSD2 Bitmap Horizontal Size MSB (R/W) [BMAPHSIZE2] BmapHSize2H Reserved <1:0> <7:2> Bits<9:8> of OSD1 bitmap horizontal size Reserved A6 OSD2 Bitmap Horizontal Total Pixels LSB (R/W) [BMAPHTOTAL2] BmapHTotal2L <7:0> Bits<7:0> of OSD2 bitmap horizontal total (Unit: 1 OSD pixel) A7 OSD2 Bitmap Horizontal Total Pixels MSB (R/W) [BMAPHTOTAL2] BmapHTotal2H Reserved <1:0> <7:2> Bits<9:8> of OSD2 bitmap horizontal total Reserved A8 OSD2 Bitmap Vertical Size LSB (R/W) [BMAPVSIZE2] BmapVSize2L <7:0> Bits<7:0> of OSD2 bitmap vertical size (Unit: 1 OSD line) (c)2002,2003-Copyright by AverLogic Technologies, Corp. Version B1.0 69 AL260 A9 OSD2 Bitmap Vertical Size MSB (R/W) [BMAPVSIZE2] BmapVSize2H Reserved AA <1:0> <7:2> Bits<9:8> of OSD2 bitmap vertical size Reserved OSD2 Bitmap Vertical total Lines LSB (R/W) [BMAPVTOTAL2] BmapVTotal2L <7:0> Bits<7:0> of OSD2 bitmap vertical total(Unit: 1 OSD line) AB OSD2 Bitmap Vertical Total Lines MSB (R/W) [BMAPVTOTAL2] BmapVTotal2H Reserved <1:0> <7:2> Bits<9:8> of OSD2 bitmap vertical total Reserved AC OSD2 Icon Horizontal Total (R/W) [ICONHTOTAL2] IconHtotal2 <7:0> OSD2 horizontal icon total (Unit: 1 icon) AD OSD2 Icon Vertical Total (R/W) [ICONVTOTAL2] IconVTotal2 <7:0> OSD2 vertical icon total (Unit: 1 icon) AF OSD2 Font Line Size (R/W) [FONTLINESIZE2] Fontlinesize2 <7:0> memory size of a line of font (Unit: 1 byte) VIII. Desktop Color Registers B3 Desktop Color Component Red (R/W) [DESKR] DeskColorRed <7:0> Desktop color red B4 Desktop Color Component Green (R/W) [DESKG] DeskColorGreen <7:0> Desktop color green B5 Desktop Color Component Blue (R/W) [DESKB] DeskColorBlue <7:0> Desktop color blue IX. Film Detection/Motion Adaptive Registers C4 Motion Pixels Threshold LSB (R/W) [MOTIONCNTTH] (c)2002,2003-Copyright by AverLogic Technologies, Corp. Version B1.0 70 AL260 MvCntThL C5 <7:0> Bit<7:0> of motion counter threshold Motion Pixels Threshold MSB (R/W) [MOTIONCNTTH] MvCntThH <7:0> Bit<15:8> of motion counter threshold C6 Lumina(Y) Threshold (R/W) [LUMATH] YThL Reserved <6:0> <7> Y threshold for film & motion compensation Reserved C7 Chroma(C) Threshold (R/W) [CHROMATH] CThH Reserved <6:0> <7> C threshold for film & motion compensation Reserved C8 De-interlacing Control Register(R/W) [MCCTRL] MCEn <0> Motion Compensation Enable 0 1 MvMode <1> 0 1 Reserved TestMv Reserved <2> <3> <7:4> Field Merge De-interlace Mode Motion Adaptive De-interlace Mode Y/C Comparison Y Comparison Only Motion Estimation Type Reserved Display Motion Part Reserved C9 Film Detection Control Register(R/W) [FILMCTRL] FilmDetEn <0> Film detection enable 0 1 ResetType <1> 0 1 FilmReset <2> 0 1 Disable Enable H/W Auto Detection S/W Reset to Non-Film after Film Detected Disable Reset Reset when bit 1 is turn on Non-Film Detection Type Reset Film Detection, depending on bit1 (c)2002,2003-Copyright by AverLogic Technologies, Corp. Version B1.0 71 AL260 Reserved PdMatch CE <3> <7:4> Reserved Number of film sequence matched Motion Pixel Numbers LSB (R) [MVCNT] MvCountL <7:0> Bit<7:0> of pixels numbers of difference between 2-field/frame CF Motion Pixel Numbers MSB (R) [MVCNT] MvCountH <7:0> Bit<15:8> of pixels numbers of difference between 2-field/frame X. Keystone/Sharpness Registers CB Keyston/Sharpness Control Register(R/W) [SHPKEYCTRL] ShapEn <0> Sharpness enable 0 1 KeyEn <4> 0 1 Interlace EvenField TriLevel C0 <5> <6> <7> Disable Enable Disable Enable Keystone enable Interlace output enable Even field mode Tri level analog data output enable Keystone Parameters Address LSB (R/W) [KEYADDR] KeyAddrL <7:0> Bit<7:0> of keystone FIFO address C1 Keystone Parameters Address MSB (R/W) [KEYADDR] KeyAddrH Reserved KeyWriteEn <3:0> <6:4> <7> Bit<11:8> of keystone FIFO address Reserved Keystone fifo write enable 0 1 Disable Enable Note: Keystone parameter for each scan line is stored into 1280x32 SRAM inside AL310. KeyAddr is the address of read/write pointer of this SRAM. (c)2002,2003-Copyright by AverLogic Technologies, Corp. Version B1.0 72 AL260 XI. Tri-Level Sync Registers D0 Tri Level Sync Parameter (W) [TRISYNCA] PeriodA <7:0> Tri level sync parameter Period_a D1 Tri Level Sync Parameter (W) [TRISYNCB] PeriodB <7:0> Tri level sync parameter Period_a D2 Tri Level Sync Parameter (W) [TRISYNCD1] Delta1 Reserved <6:0> <7> Bit<6> is sign bit ex. 60h means from blank_level , - 32 every unit Reserved D3 Tri Level Sync Parameter (W) [TRISYNCD2] Delta2 Reserved <6:0> <7> Bit<6> is sign bit ex. 20h means from sync_level, + 32 every unit Reserved D4 Tri Level Sync Parameter (W) [TRISYNBLANK] BlankData <7:0> Data of blanking period D7 Tri Level Sync Parameter (W) [TRISYNCLEVEL] SyncLevel <7:0> Sync level value XIII. Display Parameter Registers C2 Tune Display Horizontal Sync Phase (R/W) [DISTUNEHS] DisHsDelay CC <4:0> Output horizontal sync delay (Unit: 1 oclk) Tune Display Pixel Clock Phase (R/W) [DISTUNESCLK] TuneSclk <2:0> <4:3> Phase delay number(8 steps) Phase delay types 00 Sclk (c)2002,2003-Copyright by AverLogic Technologies, Corp. Version B1.0 73 AL260 01 10 11 Reserved CA <7:5> Sclk + delay phase Inversed Sclk Inversed Sclk + delay phase Reserved Phase Detection Control Register(R/W) [PHASECTRL] PhaseEn <0> Phase detection Enable 0 1 PhaseMode <2:1> 00 01 10 11 Reserved <7:3> Disable Enable 8-bit comparison 7-bit comparison 6-bit comparison 5-bit comparison Phase detection precision Tie to "00110" D7 Display Horizontal Total Counter LSB (R) [DISHTOTALCNT] HTotalCntL <7:0> Bit<7:0> of display horizontal total count D8 Display Horizontal Total Counter MSB (R) [DISHTOTALCNT] HTotalCntH Reserved <2:0> <7:3> Bit<10:8> of display horizontal total count Reserved D9 Display Vertical Total Counter LSB (R) [DISVTOTALCNT] VTotalCntL <7:0> Bit<7:0> of display vertical total count DA Display Vertical Total Counter MSB (R) [DISVTOTALCNT] VTotalCntH Reserved <2:0> <7:3> Bit<10:8> of display vertical total count Reserved DB Phase Counter LSB (R) [PHASECNT] PhaseCntL <7:0> Bit<7:0> of phase count value DC Phase Counter MSB (R) [PHASECNT] (c)2002,2003-Copyright by AverLogic Technologies, Corp. Version B1.0 74 AL260 PhaseCntH Reserved F0 <4:0> <7:5> Bit<12:8> of phase count value Reserved Enable Brightness/Contrast/Saturation (W) [DISADJEN] PanelAdjEn Reserved <0> <7:1> Enable brightness/contrast/saturation Reserved F1 Brightness Value (W) [BRIGHTNESS] Brightness <7:0> Brightness value, Default: "80" F2 Contrast Value (W) [CONTRAST] Contrast <7:0> Contrast value, Default: "40" F3 Saturation Value (W) [SATURATION] Saturation <7:0> Saturation value, Default: "40" (c)2002,2003-Copyright by AverLogic Technologies, Corp. Version B1.0 75 AL260 10 Electrical Characteristics 10.1 Absolute Maximum Ratings (Excessive ratings are harmful to the lifetime. Only for user guidelines, not tested.) Parameter VDD VP IO TAMB Tstg TVSOL Supply Voltage Input Pin Voltage Output Current Ambient Op. Temperature Storage Temperature Vapor Phase Soldering 3.3V Rating -0.3 ~ +3.8 -0.3 ~ +(VDD+0.3) -20 ~ +20 0 ~ +85 -40 ~ +125 220 Unit V V mA C C C Temperature (15 Sec.) 10.2 Recommended Operating Conditions 3.3V Rating Min. Typical +3.3 Max. +3.6 VDD 0.3 VDD +70 V V V C Parameter Unit VDD VIH VIL TAMB Supply Voltage High Level Input Voltage Low Level Input Voltage Ambient Op. Temperature +3.0 0.7 VDD 0 0 10.3 DC Characteristics (VDD = 3.3V, Vss=0V. TAMB = 0 to 70C; Some parameters are guaranteed by design only, not production tested) Parameter Min. 3.3V Rating Typical Max. Unit (c)2002,2003-Copyright by AverLogic Technologies, Corp. Version B1.0 76 AL260 Parameter Min. VIH VIL VOH VOL ILI ILO Hi-level Input Voltage Lo-level Input Voltage Hi-level Output Voltage Lo-level Output Voltage Input Leakage Current Output Leakage Current 0.7 VDD 0 2.4 -5 -5 3.3V Rating Typical Max. VDD 0.3 VDD VDD +0.4 +5 +5 Unit V V V V A A 10.4 AC Characteristics (VDD = 3.3V, Vss=0V, TAMB = 0 to 70C; Some parameters are guaranteed by design only, not production tested) (c)2002,2003-Copyright by AverLogic Technologies, Corp. Version B1.0 77 AL260 11 Timing Diagrams TBD. (c)2002,2003-Copyright by AverLogic Technologies, Corp. Version B1.0 78 AL260 12 Mechanical Drawing- PQFP-208 (c)2002,2003-Copyright by AverLogic Technologies, Corp. Version B1.0 79 AL260 CONTACT INFORMATION Averlogic Technologies Corp. 4F, No. 514, Sec. 2, Cheng Kung Rd., Nei-Hu Dist., Taipei, Taiwan Tel: +886 2-27915050 Fax: +886 2-27912132 E-mail: sales@averlogic.com.tw URL: http://www.averlogic.com.tw Averlogic Technologies, Inc. 90 Great Oaks Blvd. #204, San Jose, CA 95119, U.S.A. Tel: 1 408 361-0400 Fax: 1 408 361-0404 E-mail: sales@averlogic.com URL: http://www.averlogic.com (c)2002,2003-Copyright by AverLogic Technologies, Corp. Version B1.0 80 |
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